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ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
c94eefb258
commit
fb8989e640
@ -215,8 +215,6 @@ namespace {
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const { return 0; }
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unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
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const { return 0; }
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unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
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@ -2024,7 +2024,8 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
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Srl_imm)) {
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assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
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unsigned Width = CountTrailingOnes_32(And_imm);
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// Note: The width operand is encoded as width-1.
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unsigned Width = CountTrailingOnes_32(And_imm) - 1;
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unsigned LSB = Srl_imm;
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SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
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SDValue Ops[] = { N->getOperand(0).getOperand(0),
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@ -2044,7 +2045,8 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
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unsigned Srl_imm = 0;
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if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
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assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
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unsigned Width = 32 - Srl_imm;
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// Note: The width operand is encoded as width-1.
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unsigned Width = 32 - Srl_imm - 1;
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int LSB = Srl_imm - Shl_imm;
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if (LSB < 0)
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return NULL;
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@ -513,14 +513,6 @@ def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
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let ParserMatchClass = Imm0_31AsmOperand;
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}
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/// imm0_31_m1 - Matches and prints like imm0_31, but encodes as 'value - 1'.
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def imm0_31_m1 : Operand<i32>, ImmLeaf<i32, [{
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return Imm >= 0 && Imm < 32;
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}]> {
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let EncoderMethod = "getImmMinusOneOpValue";
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let DecoderMethod = "DecodeImmMinusOneOperand";
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}
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// imm0_65535_expr - For movt/movw - 16-bit immediate that can also reference
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// a relocatable expression.
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//
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@ -2423,7 +2415,7 @@ def UXTAB16 : AI_exta_rrot_np<0b01101100, "uxtab16">;
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def SBFX : I<(outs GPR:$Rd),
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(ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
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(ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
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AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
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"sbfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
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Requires<[IsARM, HasV6T2]> {
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@ -2440,7 +2432,7 @@ def SBFX : I<(outs GPR:$Rd),
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}
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def UBFX : I<(outs GPR:$Rd),
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(ins GPR:$Rn, imm0_31:$lsb, imm0_31_m1:$width),
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(ins GPR:$Rn, imm0_31:$lsb, imm1_32:$width),
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AddrMode1, 4, IndexModeNone, DPFrm, IIC_iUNAsi,
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"ubfx", "\t$Rd, $Rn, $lsb, $width", "", []>,
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Requires<[IsARM, HasV6T2]> {
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@ -2024,7 +2024,7 @@ def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm),
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}
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def t2SBFX: T2TwoRegBitFI<
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(outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
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(outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
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IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 1;
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@ -2033,7 +2033,7 @@ def t2SBFX: T2TwoRegBitFI<
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}
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def t2UBFX: T2TwoRegBitFI<
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(outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm0_31_m1:$msb),
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(outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb),
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IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> {
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let Inst{31-27} = 0b11110;
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let Inst{25} = 1;
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@ -2605,6 +2605,15 @@ validateInstruction(MCInst &Inst,
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"source operands must be sequential");
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return false;
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}
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case ARM::SBFX:
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case ARM::UBFX: {
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// width must be in range [1, 32-lsb]
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unsigned lsb = Inst.getOperand(2).getImm();
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unsigned widthm1 = Inst.getOperand(3).getImm();
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if (widthm1 >= 32 - lsb)
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return Error(Operands[5]->getStartLoc(),
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"bitfield width must be in range [1,32-lsb]");
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}
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}
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return false;
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@ -1026,7 +1026,7 @@ static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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decodeRm(insn))));
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MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 7)));
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MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16) + 1));
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MI.addOperand(MCOperand::CreateImm(slice(insn, 20, 16)));
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OpIdx += 3;
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return true;
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}
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@ -1698,7 +1698,7 @@ static bool DisassembleThumb2DPBinImm(MCInst &MI, unsigned Opcode,
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assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX)
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&& "Unexpected opcode");
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MI.addOperand(MCOperand::CreateImm(getLsb(insn)));
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MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1));
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MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn)));
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++OpIdx;
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}
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@ -259,11 +259,6 @@ public:
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unsigned getT2SORegOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const;
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unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return MI.getOperand(Op).getImm() - 1;
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}
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unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return 64 - MI.getOperand(Op).getImm();
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@ -1308,6 +1308,16 @@ _func:
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@ CHECK: sbc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xc6,0xe0]
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@------------------------------------------------------------------------------
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@ SBFX
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@------------------------------------------------------------------------------
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sbfx r4, r5, #16, #1
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sbfxgt r4, r5, #16, #16
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@ CHECK: sbfx r4, r5, #16, #1 @ encoding: [0x55,0x48,0xa0,0xe7]
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@ CHECK: sbfxgt r4, r5, #16, #16 @ encoding: [0x55,0x48,0xaf,0xc7]
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@------------------------------------------------------------------------------
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@ SEL
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@------------------------------------------------------------------------------
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@ -2001,3 +2011,11 @@ _func:
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@ CHECK: uasxeq r9, r12, r0 @ encoding: [0x30,0x9f,0x5c,0x06]
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@------------------------------------------------------------------------------
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@ UBFX
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@------------------------------------------------------------------------------
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ubfx r4, r5, #16, #1
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ubfxgt r4, r5, #16, #16
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@ CHECK: ubfx r4, r5, #16, #1 @ encoding: [0x55,0x48,0xe0,0xe7]
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@ CHECK: ubfxgt r4, r5, #16, #16 @ encoding: [0x55,0x48,0xef,0xc7]
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@ -272,3 +272,14 @@
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@ CHECK-ERRORS: error: rotate operator 'ror' expected
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@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: ^
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@ Out of range width for SBFX/UBFX
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sbfx r4, r5, #31, #2
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ubfxgt r4, r5, #16, #17
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@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
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@ CHECK-ERRORS: sbfx r4, r5, #31, #2
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: bitfield width must be in range [1,32-lsb]
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@ CHECK-ERRORS: ubfxgt r4, r5, #16, #17
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@ CHECK-ERRORS: ^
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