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1. In ppc64 mode we need only use one GPR.

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2. Float values need to be promoted to double when they are vararg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32074 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Laskey 2006-12-01 16:30:47 +00:00
parent 45e507ca9b
commit fbb74e6941
1 changed files with 7 additions and 1 deletions
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8
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -1377,6 +1377,12 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
break;
case MVT::f32:
case MVT::f64:
if (isVarArg && isPPC64) {
// Float varargs need to be promoted to double.
if (Arg.getValueType() == MVT::f32)
Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
}
if (FPR_idx != NumFPRs) {
RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
@ -1390,7 +1396,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
MemOpChains.push_back(Load.getValue(1));
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
}
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);