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[X86] Add test case I forgot to commit with r312285.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312335 91177308-0d34-0410-b5e6-96231b3b80d8
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49
test/CodeGen/X86/pr34381.ll
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49
test/CodeGen/X86/pr34381.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=slow-incdec -fast-isel -O0 | FileCheck %s
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@var_21 = external constant i32, align 4
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@var_29 = external constant i8, align 1
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@var_390 = external global i32, align 4
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@var_11 = external constant i8, align 1
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@var_370 = external global i8, align 1
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; Function Attrs: noinline nounwind optnone uwtable
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define void @_Z3foov() {
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; CHECK-LABEL: _Z3foov:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl {{.*}}(%rip), %eax
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; CHECK-NEXT: movsbl {{.*}}(%rip), %ecx
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; CHECK-NEXT: negl %ecx
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; CHECK-NEXT: subl %ecx, %eax
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; CHECK-NEXT: setb %dl
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; CHECK-NEXT: addb $-1, %dl
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; CHECK-NEXT: sete %sil
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; CHECK-NEXT: movzbl %sil, %ecx
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; CHECK-NEXT: movl %ecx, {{.*}}(%rip)
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; CHECK-NEXT: movb {{.*}}(%rip), %sil
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; CHECK-NEXT: movsbl %sil, %ecx
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; CHECK-NEXT: movw %cx, %di
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; CHECK-NEXT: movb %dil, %sil
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; CHECK-NEXT: movb %sil, var_370
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; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) # 4-byte Spill
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; CHECK-NEXT: movb %dl, -{{[0-9]+}}(%rsp) # 1-byte Spill
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; CHECK-NEXT: retq
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entry:
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%0 = load i32, i32* @var_21, align 4
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%1 = load i8, i8* @var_29, align 1
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%conv = sext i8 %1 to i32
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%sub = sub nsw i32 0, %conv
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%cmp = icmp ult i32 %0, %sub
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%conv1 = zext i1 %cmp to i32
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%add = add nsw i32 %conv1, -1
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%conv2 = trunc i32 %add to i8
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%tobool = icmp ne i8 %conv2, 0
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%lnot = xor i1 %tobool, true
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%conv3 = zext i1 %lnot to i32
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store i32 %conv3, i32* @var_390, align 4
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%2 = load i8, i8* @var_11, align 1
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%conv4 = sext i8 %2 to i16
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%conv5 = trunc i16 %conv4 to i8
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store i8 %conv5, i8* @var_370, align 1
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ret void
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}
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