[X86] Add test case I forgot to commit with r312285.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312335 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2017-09-01 16:40:24 +00:00
parent 043998b329
commit fc13e66509

View File

@ -0,0 +1,49 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=slow-incdec -fast-isel -O0 | FileCheck %s
@var_21 = external constant i32, align 4
@var_29 = external constant i8, align 1
@var_390 = external global i32, align 4
@var_11 = external constant i8, align 1
@var_370 = external global i8, align 1
; Function Attrs: noinline nounwind optnone uwtable
define void @_Z3foov() {
; CHECK-LABEL: _Z3foov:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
; CHECK-NEXT: movsbl {{.*}}(%rip), %ecx
; CHECK-NEXT: negl %ecx
; CHECK-NEXT: subl %ecx, %eax
; CHECK-NEXT: setb %dl
; CHECK-NEXT: addb $-1, %dl
; CHECK-NEXT: sete %sil
; CHECK-NEXT: movzbl %sil, %ecx
; CHECK-NEXT: movl %ecx, {{.*}}(%rip)
; CHECK-NEXT: movb {{.*}}(%rip), %sil
; CHECK-NEXT: movsbl %sil, %ecx
; CHECK-NEXT: movw %cx, %di
; CHECK-NEXT: movb %dil, %sil
; CHECK-NEXT: movb %sil, var_370
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) # 4-byte Spill
; CHECK-NEXT: movb %dl, -{{[0-9]+}}(%rsp) # 1-byte Spill
; CHECK-NEXT: retq
entry:
%0 = load i32, i32* @var_21, align 4
%1 = load i8, i8* @var_29, align 1
%conv = sext i8 %1 to i32
%sub = sub nsw i32 0, %conv
%cmp = icmp ult i32 %0, %sub
%conv1 = zext i1 %cmp to i32
%add = add nsw i32 %conv1, -1
%conv2 = trunc i32 %add to i8
%tobool = icmp ne i8 %conv2, 0
%lnot = xor i1 %tobool, true
%conv3 = zext i1 %lnot to i32
store i32 %conv3, i32* @var_390, align 4
%2 = load i8, i8* @var_11, align 1
%conv4 = sext i8 %2 to i16
%conv5 = trunc i16 %conv4 to i8
store i8 %conv5, i8* @var_370, align 1
ret void
}