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[mips] Emit two CFI offset directives per double precision SDC1/LDC1
instead of just one for FR=1 registers Differential Revision: http://reviews.llvm.org/D4310 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212769 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -26,9 +26,9 @@ def RetCC_MipsO32 : CallingConv<[
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// f32 are returned in registers F0, F2
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CCIfType<[f32], CCAssignToReg<[F0, F2]>>,
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// f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or
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// f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or
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// in D0 and D1 in FP32bit mode.
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CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>,
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CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>,
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CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>>
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]>;
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@ -247,8 +247,9 @@ def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
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def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_O32_FP64 :
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CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
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(sequence "S%u", 7, 0))>;
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def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
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D30_64, RA_64, FP_64, GP_64,
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@ -343,6 +343,22 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
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MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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} else if (Mips::FGR64RegClass.contains(Reg)) {
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unsigned Reg0 = MRI->getDwarfRegNum(Reg, true);
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unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1;
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if (!STI.isLittle())
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std::swap(Reg0, Reg1);
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unsigned CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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CFIIndex = MMI.addFrameInst(
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MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
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BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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} else {
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// Reg is either in GPR32 or FGR32.
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unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
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@ -10,6 +10,9 @@
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; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
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; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -mattr=-n64,+n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s
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; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
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; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s
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; Test the float returns for all ABI's and byte orders as specified by
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; section 5 of MD00305 (MIPS ABIs Described).
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@ -44,3 +47,13 @@ entry:
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; N32-DAG: ldc1 $f0, %lo(double)([[R1:\$[0-9]+]])
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; N64-DAG: ld [[R1:\$[0-9]+]], %got_disp(double)($1)
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; N64-DAG: ldc1 $f0, 0([[R1]])
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define { double, double } @retComplexDouble() #0 {
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%retval = alloca { double, double }, align 8
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%1 = load { double, double }* %retval
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ret { double, double } %1
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}
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; ALL-LABEL: retComplexDouble:
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; 032FP64-DAG: ldc1 $f0, 0($sp)
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; 032FP64-DAG: ldc1 $f2, 8($sp)
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41
test/CodeGen/Mips/cfi_offset.ll
Normal file
41
test/CodeGen/Mips/cfi_offset.ll
Normal file
@ -0,0 +1,41 @@
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; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB
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; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL
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; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB
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; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL
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; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB
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; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL
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@var = global double 0.0
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declare void @foo(...)
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define void @bar() {
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; CHECK-LABEL: bar:
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; CHECK: .cfi_def_cfa_offset 40
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; CHECK: sdc1 $f22, 32($sp)
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; CHECK: sdc1 $f20, 24($sp)
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; CHECK: sw $ra, 20($sp)
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; CHECK: sw $16, 16($sp)
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; CHECK-EB: .cfi_offset 55, -8
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; CHECK-EB: .cfi_offset 54, -4
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; CHECK-EB: .cfi_offset 53, -16
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; CHECK-EB: .cfi_offset 52, -12
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; CHECK-EL: .cfi_offset 54, -8
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; CHECK-EL: .cfi_offset 55, -4
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; CHECK-EL: .cfi_offset 52, -16
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; CHECK-EL: .cfi_offset 53, -12
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; CHECK: .cfi_offset 31, -20
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; CHECK: .cfi_offset 16, -24
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%val1 = load volatile double* @var
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%val2 = load volatile double* @var
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call void (...)* @foo() nounwind
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store volatile double %val1, double* @var
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store volatile double %val2, double* @var
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ret void
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}
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