RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2024-12-20 19:20:23 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Fix missing relocation for TLS addressing peephole optimization.

Browse Source 
Report and fix due to Kai Nacke.  Testcase update by me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176029 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt 2013-02-25 16:44:35 +00:00
parent 7e6ffac9ab
commit fc7695a653
3 changed files with 15 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
include/llvm/Support/ELF.h
View File

@ -483,6 +483,7 @@ enum {
R_PPC64_TOC16_DS = 63,
R_PPC64_TOC16_LO_DS = 64,
R_PPC64_TLS = 67,
R_PPC64_TPREL16_LO = 70,
R_PPC64_DTPREL16_LO = 75,
R_PPC64_DTPREL16_HA = 77,
R_PPC64_GOT_TLSGD16_LO = 80,

3
lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
View File

@ -153,6 +153,9 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
case PPC::fixup_ppc_toc16:
switch (Modifier) {
default: llvm_unreachable("Unsupported Modifier");
case MCSymbolRefExpr::VK_PPC_TPREL16_LO:
Type = ELF::R_PPC64_TPREL16_LO;
break;
case MCSymbolRefExpr::VK_PPC_DTPREL16_LO:
Type = ELF::R_PPC64_DTPREL16_LO;
break;

17
test/CodeGen/PowerPC/tls.ll
View File

@ -1,16 +1,21 @@
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-freebsd10.0"
; RUN: llc -O0 < %s -march=ppc64 | FileCheck %s
; RUN: llc -O0 < %s -march=ppc64 | FileCheck -check-prefix=OPT0 %s
; RUN: llc -O1 < %s -march=ppc64 | FileCheck -check-prefix=OPT1 %s
@a = thread_local global i32 0, align 4
;CHECK: localexec:
;OPT0: localexec:
;OPT1: localexec:
define i32 @localexec() nounwind {
entry:
;CHECK: addis [[REG1:[0-9]+]], 13, a@tprel@ha
;CHECK-NEXT: li [[REG2:[0-9]+]], 42
;CHECK-NEXT: addi [[REG1]], [[REG1]], a@tprel@l
;CHECK-NEXT: stw [[REG2]], 0([[REG1]])
;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha
;OPT0-NEXT: li [[REG2:[0-9]+]], 42
;OPT0-NEXT: addi [[REG1]], [[REG1]], a@tprel@l
;OPT0-NEXT: stw [[REG2]], 0([[REG1]])
;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha
;OPT1-NEXT: li [[REG2:[0-9]+]], 42
;OPT1-NEXT: stw [[REG2]], a@tprel@l([[REG1]])
store i32 42, i32* @a, align 4
ret i32 0
}