From fd22980d6b57b358204eb9b511e9da3838ae021f Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Sat, 19 Jul 2014 18:15:16 +0000
Subject: [PATCH] R600: Implement a few simple TTI queries.

I'm not sure if these have any effect right now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213455 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/R600/AMDGPUTargetTransformInfo.cpp | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/lib/Target/R600/AMDGPUTargetTransformInfo.cpp b/lib/Target/R600/AMDGPUTargetTransformInfo.cpp
index e3a546e1d72..88934b65876 100644
--- a/lib/Target/R600/AMDGPUTargetTransformInfo.cpp
+++ b/lib/Target/R600/AMDGPUTargetTransformInfo.cpp
@@ -79,6 +79,10 @@ public:
 
   PopcntSupportKind getPopcntSupport(unsigned IntTyWidthInBit) const override;
 
+  unsigned getNumberOfRegisters(bool Vector) const override;
+  unsigned getRegisterBitWidth(bool Vector) const override;
+  unsigned getMaximumUnrollFactor() const override;
+
   /// @}
 };
 
@@ -127,3 +131,23 @@ AMDGPUTTI::getPopcntSupport(unsigned TyWidth) const {
   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
   return ST->hasBCNT(TyWidth) ? PSK_FastHardware : PSK_Software;
 }
+
+unsigned AMDGPUTTI::getNumberOfRegisters(bool Vec) const {
+  if (Vec)
+    return 0;
+
+  // Number of VGPRs on SI.
+  if (ST->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
+    return 256;
+
+  return 4 * 128; // XXX - 4 channels. Should these count as vector instead?
+}
+
+unsigned AMDGPUTTI::getRegisterBitWidth(bool) const {
+  return 32;
+}
+
+unsigned AMDGPUTTI::getMaximumUnrollFactor() const {
+  // Semi-arbitrary large amount.
+  return 64;
+}