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R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216220 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
5f52739370
commit
fdbf61d00d
@ -1367,6 +1367,88 @@ void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
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}
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}
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void SIInstrInfo::splitSMRD(MachineInstr *MI,
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const TargetRegisterClass *HalfRC,
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unsigned HalfImmOp, unsigned HalfSGPROp,
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MachineInstr *&Lo, MachineInstr *&Hi) const {
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DebugLoc DL = MI->getDebugLoc();
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MachineBasicBlock *MBB = MI->getParent();
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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unsigned RegLo = MRI.createVirtualRegister(HalfRC);
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unsigned RegHi = MRI.createVirtualRegister(HalfRC);
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unsigned HalfSize = HalfRC->getSize();
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const MachineOperand *OffOp =
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getNamedOperand(*MI, AMDGPU::OpName::offset);
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const MachineOperand *SBase = getNamedOperand(*MI, AMDGPU::OpName::sbase);
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if (OffOp) {
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// Handle the _IMM variant
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unsigned LoOffset = OffOp->getImm();
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unsigned HiOffset = LoOffset + (HalfSize / 4);
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Lo = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegLo)
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.addOperand(*SBase)
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.addImm(LoOffset);
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if (!isUInt<8>(HiOffset)) {
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unsigned OffsetSGPR =
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MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(*MBB, MI, DL, get(AMDGPU::S_MOV_B32), OffsetSGPR)
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.addImm(HiOffset << 2); // The immediate offset is in dwords,
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// but offset in register is in bytes.
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Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegHi)
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.addOperand(*SBase)
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.addReg(OffsetSGPR);
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} else {
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Hi = BuildMI(*MBB, MI, DL, get(HalfImmOp), RegHi)
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.addOperand(*SBase)
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.addImm(HiOffset);
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}
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} else {
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// Handle the _SGPR variant
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MachineOperand *SOff = getNamedOperand(*MI, AMDGPU::OpName::soff);
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Lo = BuildMI(*MBB, MI, DL, get(HalfSGPROp), RegLo)
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.addOperand(*SBase)
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.addOperand(*SOff);
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unsigned OffsetSGPR = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(*MBB, MI, DL, get(AMDGPU::S_ADD_I32), OffsetSGPR)
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.addOperand(*SOff)
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.addImm(HalfSize);
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Hi = BuildMI(*MBB, MI, DL, get(HalfSGPROp))
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.addOperand(*SBase)
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.addReg(OffsetSGPR);
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}
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unsigned SubLo, SubHi;
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switch (HalfSize) {
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case 4:
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SubLo = AMDGPU::sub0;
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SubHi = AMDGPU::sub1;
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break;
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case 8:
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SubLo = AMDGPU::sub0_sub1;
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SubHi = AMDGPU::sub2_sub3;
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break;
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case 16:
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SubLo = AMDGPU::sub0_sub1_sub2_sub3;
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SubHi = AMDGPU::sub4_sub5_sub6_sub7;
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break;
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case 32:
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SubLo = AMDGPU::sub0_sub1_sub2_sub3_sub4_sub5_sub6_sub7;
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SubHi = AMDGPU::sub8_sub9_sub10_sub11_sub12_sub13_sub14_sub15;
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break;
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default:
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llvm_unreachable("Unhandled HalfSize");
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}
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BuildMI(*MBB, MI, DL, get(AMDGPU::REG_SEQUENCE))
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.addOperand(MI->getOperand(0))
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.addReg(RegLo)
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.addImm(SubLo)
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.addReg(RegHi)
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.addImm(SubHi);
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}
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void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
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MachineBasicBlock *MBB = MI->getParent();
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switch (MI->getOpcode()) {
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@ -1375,7 +1457,7 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
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case AMDGPU::S_LOAD_DWORDX2_IMM:
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case AMDGPU::S_LOAD_DWORDX2_SGPR:
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case AMDGPU::S_LOAD_DWORDX4_IMM:
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case AMDGPU::S_LOAD_DWORDX4_SGPR:
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case AMDGPU::S_LOAD_DWORDX4_SGPR: {
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unsigned NewOpcode = getVALUOp(*MI);
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unsigned RegOffset;
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unsigned ImmOffset;
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@ -1422,14 +1504,44 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
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.addImm(AMDGPU::sub2)
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.addReg(DWord3)
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.addImm(AMDGPU::sub3);
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MI->setDesc(get(NewOpcode));
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if (MI->getOperand(2).isReg()) {
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MI->getOperand(2).setReg(MI->getOperand(1).getReg());
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} else {
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MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
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}
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MI->getOperand(1).setReg(SRsrc);
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MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
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MI->setDesc(get(NewOpcode));
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if (MI->getOperand(2).isReg()) {
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MI->getOperand(2).setReg(MI->getOperand(1).getReg());
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} else {
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MI->getOperand(2).ChangeToRegister(MI->getOperand(1).getReg(), false);
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}
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MI->getOperand(1).setReg(SRsrc);
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MI->addOperand(*MBB->getParent(), MachineOperand::CreateImm(ImmOffset));
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const TargetRegisterClass *NewDstRC =
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RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass);
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unsigned DstReg = MI->getOperand(0).getReg();
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unsigned NewDstReg = MRI.createVirtualRegister(NewDstRC);
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MRI.replaceRegWith(DstReg, NewDstReg);
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break;
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}
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case AMDGPU::S_LOAD_DWORDX8_IMM:
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case AMDGPU::S_LOAD_DWORDX8_SGPR: {
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MachineInstr *Lo, *Hi;
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splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
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AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
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MI->eraseFromParent();
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moveSMRDToVALU(Lo, MRI);
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moveSMRDToVALU(Hi, MRI);
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break;
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}
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case AMDGPU::S_LOAD_DWORDX16_IMM:
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case AMDGPU::S_LOAD_DWORDX16_SGPR: {
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MachineInstr *Lo, *Hi;
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splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
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AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);
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MI->eraseFromParent();
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moveSMRDToVALU(Lo, MRI);
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moveSMRDToVALU(Hi, MRI);
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break;
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}
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}
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}
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@ -170,6 +170,12 @@ public:
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/// create new instruction and insert them before \p MI.
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void legalizeOperands(MachineInstr *MI) const;
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/// \brief Split an SMRD instruction into two smaller loads of half the
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// size storing the results in \p Lo and \p Hi.
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void splitSMRD(MachineInstr *MI, const TargetRegisterClass *HalfRC,
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unsigned HalfImmOp, unsigned HalfSGPROp,
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MachineInstr *&Lo, MachineInstr *&Hi) const;
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void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const;
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/// \brief Replace this instruction's opcode with the equivalent VALU
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@ -88,3 +88,31 @@ entry:
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store i32 %3, i32 addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: @s_load_imm_v8i32
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; CHECK: BUFFER_LOAD_DWORDX4
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; CHECK: BUFFER_LOAD_DWORDX4
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define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
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%tmp1 = getelementptr inbounds i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
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%tmp3 = load <8 x i32> addrspace(2)* %tmp2, align 4
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store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
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ret void
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}
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; CHECK-LABEL: @s_load_imm_v16i32
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; CHECK: BUFFER_LOAD_DWORDX4
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; CHECK: BUFFER_LOAD_DWORDX4
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; CHECK: BUFFER_LOAD_DWORDX4
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; CHECK: BUFFER_LOAD_DWORDX4
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define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) {
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entry:
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%tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
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%tmp1 = getelementptr inbounds i32 addrspace(2)* %in, i32 %tmp0
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%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
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%tmp3 = load <16 x i32> addrspace(2)* %tmp2, align 4
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store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
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ret void
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}
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