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Pull utility routines with no SelectionDAG dependence out of

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SelectionDAGBuilder. FunctionLoweringInfo isn't an ideal place for
them to live, but it's better than SelectionDAGBuilder for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101267 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2010-04-14 18:31:02 +00:00
parent b02b62a271
commit fe85e76473
3 changed files with 95 additions and 76 deletions
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76
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
View File

@ -369,3 +369,79 @@ void llvm::CopyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
#endif #endif
} }
} }
/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
/// processed uses a memory 'm' constraint.
bool
llvm::hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
const TargetLowering &TLI) {
for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
InlineAsm::ConstraintInfo &CI = CInfos[i];
for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
if (CType == TargetLowering::C_Memory)
return true;
}
// Indirect operand accesses access memory.
if (CI.isIndirect)
return true;
}
return false;
}
/// getFCmpCondCode - Return the ISD condition code corresponding to
/// the given LLVM IR floating-point condition code. This includes
/// consideration of global floating-point math flags.
///
ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) {
ISD::CondCode FPC, FOC;
switch (Pred) {
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
default:
llvm_unreachable("Invalid FCmp predicate opcode!");
FOC = FPC = ISD::SETFALSE;
break;
}
if (FiniteOnlyFPMath())
return FOC;
else
return FPC;
}
/// getICmpCondCode - Return the ISD condition code corresponding to
/// the given LLVM IR integer condition code.
///
ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) {
switch (Pred) {
case ICmpInst::ICMP_EQ: return ISD::SETEQ;
case ICmpInst::ICMP_NE: return ISD::SETNE;
case ICmpInst::ICMP_SLE: return ISD::SETLE;
case ICmpInst::ICMP_ULE: return ISD::SETULE;
case ICmpInst::ICMP_SGE: return ISD::SETGE;
case ICmpInst::ICMP_UGE: return ISD::SETUGE;
case ICmpInst::ICMP_SLT: return ISD::SETLT;
case ICmpInst::ICMP_ULT: return ISD::SETULT;
case ICmpInst::ICMP_SGT: return ISD::SETGT;
case ICmpInst::ICMP_UGT: return ISD::SETUGT;
default:
llvm_unreachable("Invalid ICmp predicate opcode!");
return ISD::SETNE;
}
}

19
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.h
View File

@ -15,12 +15,15 @@
#ifndef FUNCTIONLOWERINGINFO_H #ifndef FUNCTIONLOWERINGINFO_H
#define FUNCTIONLOWERINGINFO_H #define FUNCTIONLOWERINGINFO_H
#include "llvm/InlineAsm.h"
#include "llvm/Instructions.h"
#include "llvm/ADT/APInt.h" #include "llvm/ADT/APInt.h"
#include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseMap.h"
#ifndef NDEBUG #ifndef NDEBUG
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallSet.h"
#endif #endif
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include <vector> #include <vector>
namespace llvm { namespace llvm {
@ -146,6 +149,22 @@ void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI, MachineBasicBlock *MBB);
void CopyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB, void CopyCatchInfo(BasicBlock *SrcBB, BasicBlock *DestBB,
MachineModuleInfo *MMI, FunctionLoweringInfo &FLI); MachineModuleInfo *MMI, FunctionLoweringInfo &FLI);
/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
/// processed uses a memory 'm' constraint.
bool hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
const TargetLowering &TLI);
/// getFCmpCondCode - Return the ISD condition code corresponding to
/// the given LLVM IR floating-point condition code. This includes
/// consideration of global floating-point math flags.
///
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
/// getICmpCondCode - Return the ISD condition code corresponding to
/// the given LLVM IR integer condition code.
///
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
} // end namespace llvm } // end namespace llvm
#endif #endif

76
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -972,61 +972,6 @@ static bool InBlock(const Value *V, const BasicBlock *BB) {
return true; return true;
} }
/// getFCmpCondCode - Return the ISD condition code corresponding to
/// the given LLVM IR floating-point condition code. This includes
/// consideration of global floating-point math flags.
///
static ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred) {
ISD::CondCode FPC, FOC;
switch (Pred) {
case FCmpInst::FCMP_FALSE: FOC = FPC = ISD::SETFALSE; break;
case FCmpInst::FCMP_OEQ: FOC = ISD::SETEQ; FPC = ISD::SETOEQ; break;
case FCmpInst::FCMP_OGT: FOC = ISD::SETGT; FPC = ISD::SETOGT; break;
case FCmpInst::FCMP_OGE: FOC = ISD::SETGE; FPC = ISD::SETOGE; break;
case FCmpInst::FCMP_OLT: FOC = ISD::SETLT; FPC = ISD::SETOLT; break;
case FCmpInst::FCMP_OLE: FOC = ISD::SETLE; FPC = ISD::SETOLE; break;
case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break;
case FCmpInst::FCMP_ORD: FOC = FPC = ISD::SETO; break;
case FCmpInst::FCMP_UNO: FOC = FPC = ISD::SETUO; break;
case FCmpInst::FCMP_UEQ: FOC = ISD::SETEQ; FPC = ISD::SETUEQ; break;
case FCmpInst::FCMP_UGT: FOC = ISD::SETGT; FPC = ISD::SETUGT; break;
case FCmpInst::FCMP_UGE: FOC = ISD::SETGE; FPC = ISD::SETUGE; break;
case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break;
case FCmpInst::FCMP_ULE: FOC = ISD::SETLE; FPC = ISD::SETULE; break;
case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break;
case FCmpInst::FCMP_TRUE: FOC = FPC = ISD::SETTRUE; break;
default:
llvm_unreachable("Invalid FCmp predicate opcode!");
FOC = FPC = ISD::SETFALSE;
break;
}
if (FiniteOnlyFPMath())
return FOC;
else
return FPC;
}
/// getICmpCondCode - Return the ISD condition code corresponding to
/// the given LLVM IR integer condition code.
///
static ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred) {
switch (Pred) {
case ICmpInst::ICMP_EQ: return ISD::SETEQ;
case ICmpInst::ICMP_NE: return ISD::SETNE;
case ICmpInst::ICMP_SLE: return ISD::SETLE;
case ICmpInst::ICMP_ULE: return ISD::SETULE;
case ICmpInst::ICMP_SGE: return ISD::SETGE;
case ICmpInst::ICMP_UGE: return ISD::SETUGE;
case ICmpInst::ICMP_SLT: return ISD::SETLT;
case ICmpInst::ICMP_ULT: return ISD::SETULT;
case ICmpInst::ICMP_SGT: return ISD::SETGT;
case ICmpInst::ICMP_UGT: return ISD::SETUGT;
default:
llvm_unreachable("Invalid ICmp predicate opcode!");
return ISD::SETNE;
}
}
/// EmitBranchForMergedCondition - Helper method for FindMergedConditions. /// EmitBranchForMergedCondition - Helper method for FindMergedConditions.
/// This function emits a branch and is used at the leaves of an OR or an /// This function emits a branch and is used at the leaves of an OR or an
/// AND operator tree. /// AND operator tree.
@ -5213,27 +5158,6 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// Otherwise, we couldn't allocate enough registers for this. // Otherwise, we couldn't allocate enough registers for this.
} }
/// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
/// processed uses a memory 'm' constraint.
static bool
hasInlineAsmMemConstraint(std::vector<InlineAsm::ConstraintInfo> &CInfos,
const TargetLowering &TLI) {
for (unsigned i = 0, e = CInfos.size(); i != e; ++i) {
InlineAsm::ConstraintInfo &CI = CInfos[i];
for (unsigned j = 0, ee = CI.Codes.size(); j != ee; ++j) {
TargetLowering::ConstraintType CType = TLI.getConstraintType(CI.Codes[j]);
if (CType == TargetLowering::C_Memory)
return true;
}
// Indirect operand accesses access memory.
if (CI.isIndirect)
return true;
}
return false;
}
/// visitInlineAsm - Handle a call to an InlineAsm object. /// visitInlineAsm - Handle a call to an InlineAsm object.
/// ///
void SelectionDAGBuilder::visitInlineAsm(CallSite CS) { void SelectionDAGBuilder::visitInlineAsm(CallSite CS) {