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Remove the VMOVQQ pseudo instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138177 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2011-08-20 00:52:40 +00:00
parent cbb9905d96
commit fea95c6bad
3 changed files with 8 additions and 44 deletions
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16
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -666,24 +666,24 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = ARM::VMOVD;
else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VORRq;
else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVQQ;
if (Opc) {
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (Opc == ARM::VORRq)
MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (Opc != ARM::VMOVQQ)
AddDefaultPred(MIB);
AddDefaultPred(MIB);
return;
}
// Expand the MOVQQQQ pseudo instruction in place.
if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
// Generate instructions for VMOVQQ and VMOVQQQQ pseudos in place.
if (ARM::QQPRRegClass.contains(DestReg, SrcReg) ||
ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
const TargetRegisterInfo *TRI = &getRegisterInfo();
assert(ARM::qsub_0 + 3 == ARM::qsub_3 && "Expected contiguous enum.");
for (unsigned i = ARM::qsub_0, e = ARM::qsub_3 + 1; i != e; ++i) {
unsigned EndSubReg = ARM::QQPRRegClass.contains(DestReg, SrcReg) ?
ARM::qsub_1 : ARM::qsub_3;
for (unsigned i = ARM::qsub_0, e = EndSubReg + 1; i != e; ++i) {
unsigned Dst = TRI->getSubReg(DestReg, i);
unsigned Src = TRI->getSubReg(SrcReg, i);
MachineInstrBuilder Mov =
@ -691,7 +691,7 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(Dst, RegState::Define)
.addReg(Src, getKillRegState(KillSrc))
.addReg(Src, getKillRegState(KillSrc)));
if (i == ARM::qsub_3) {
if (i == EndSubReg) {
Mov->addRegisterDefined(DestReg, TRI);
if (KillSrc)
Mov->addRegisterKilled(SrcReg, TRI);

28
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -970,34 +970,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
ExpandMOV32BitImm(MBB, MBBI);
return true;
case ARM::VMOVQQ: {
unsigned DstReg = MI.getOperand(0).getReg();
bool DstIsDead = MI.getOperand(0).isDead();
unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0);
unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1);
unsigned SrcReg = MI.getOperand(1).getReg();
bool SrcIsKill = MI.getOperand(1).isKill();
unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0);
unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1);
MachineInstrBuilder Even =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(EvenDst,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(EvenSrc, getKillRegState(SrcIsKill))
.addReg(EvenSrc, getKillRegState(SrcIsKill)));
MachineInstrBuilder Odd =
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(ARM::VORRq))
.addReg(OddDst,
RegState::Define | getDeadRegState(DstIsDead))
.addReg(OddSrc, getKillRegState(SrcIsKill))
.addReg(OddSrc, getKillRegState(SrcIsKill)));
TransferImpOps(MI, Even, Odd);
MI.eraseFromParent();
return true;
}
case ARM::VLDMQIA: {
unsigned NewOpc = ARM::VLDMDIA;
MachineInstrBuilder MIB =

8
lib/Target/ARM/ARMInstrNEON.td
View File

@ -4285,14 +4285,6 @@ def : InstAlias<"vmov${p} $Vd, $Vm",
def : InstAlias<"vmov${p} $Vd, $Vm",
(VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
let neverHasSideEffects = 1 in {
// Pseudo vector move instructions for QQ and QQQQ registers. This should
// be expanded after register allocation is completed.
def VMOVQQ : PseudoInst<(outs QQPR:$dst), (ins QQPR:$src),
NoItinerary, []>;
} // neverHasSideEffects
// VMOV : Vector Move (Immediate)
let isReMaterializable = 1 in {