RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-05-18 11:26:29 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

DAG: Remove redundant version of getRegisterTypeForCallingConv

Browse Source 
There seems to be no real reason to have these separate copies.
The existing implementations just copy each other for x86.
For Mips there is a subtle difference, which is just a bug
since it changes based on the context where which one was called.
Dropping this version, all tests pass. If I try to merge them
to match the removed version, a test fails.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@333440 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2018-05-29 17:42:26 +00:00
parent bc78b53387
commit fec5a579e7
6 changed files with 4 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
include/llvm/CodeGen/TargetLowering.h
View File

@ -1146,10 +1146,6 @@ public:
/// Certain combinations of ABIs, Targets and features require that types /// Certain combinations of ABIs, Targets and features require that types
/// are legal for some operations and not for other operations. /// are legal for some operations and not for other operations.
/// For MIPS all vector types must be passed through the integer register set. /// For MIPS all vector types must be passed through the integer register set.
virtual MVT getRegisterTypeForCallingConv(MVT VT) const {
return getRegisterType(VT);
}
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
EVT VT) const { EVT VT) const {
return getRegisterType(Context, VT); return getRegisterType(Context, VT);

4
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -778,7 +778,7 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
EVT ValueVT = ValueVTs[Value]; EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = RegCount[Value]; unsigned NumRegs = RegCount[Value];
MVT RegisterVT = IsABIMangled MVT RegisterVT = IsABIMangled
? TLI.getRegisterTypeForCallingConv(RegVTs[Value]) ? TLI.getRegisterTypeForCallingConv(*DAG.getContext(), RegVTs[Value])
: RegVTs[Value]; : RegVTs[Value];
Parts.resize(NumRegs); Parts.resize(NumRegs);
@ -877,7 +877,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG,
unsigned NumParts = RegCount[Value]; unsigned NumParts = RegCount[Value];
MVT RegisterVT = IsABIMangled MVT RegisterVT = IsABIMangled
? TLI.getRegisterTypeForCallingConv(RegVTs[Value]) ? TLI.getRegisterTypeForCallingConv(*DAG.getContext(), RegVTs[Value])
: RegVTs[Value]; : RegVTs[Value];
if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT)) if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))

6
lib/Target/Mips/MipsISelLowering.cpp
View File

@ -110,12 +110,6 @@ static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
// The MIPS MSA ABI passes vector arguments in the integer register set. // The MIPS MSA ABI passes vector arguments in the integer register set.
// The number of integer registers used is dependant on the ABI used. // The number of integer registers used is dependant on the ABI used.
MVT MipsTargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
if (VT.isVector() && Subtarget.hasMSA())
return Subtarget.isABI_O32() ? MVT::i32 : MVT::i64;
return MipsTargetLowering::getRegisterType(VT);
}
MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
EVT VT) const { EVT VT) const {
if (VT.isVector()) { if (VT.isVector()) {

4
lib/Target/Mips/MipsISelLowering.h
View File

@ -280,10 +280,6 @@ class TargetRegisterClass;
bool isCheapToSpeculateCttz() const override; bool isCheapToSpeculateCttz() const override;
bool isCheapToSpeculateCtlz() const override; bool isCheapToSpeculateCtlz() const override;
/// Return the register type for a given MVT, ensuring vectors are treated
/// as a series of gpr sized integers.
MVT getRegisterTypeForCallingConv(MVT VT) const override;
/// Return the register type for a given MVT, ensuring vectors are treated /// Return the register type for a given MVT, ensuring vectors are treated
/// as a series of gpr sized integers. /// as a series of gpr sized integers.
MVT getRegisterTypeForCallingConv(LLVMContext &Context, MVT getRegisterTypeForCallingConv(LLVMContext &Context,

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1778,12 +1778,6 @@ X86TargetLowering::getPreferredVectorAction(EVT VT) const {
return TargetLoweringBase::getPreferredVectorAction(VT); return TargetLoweringBase::getPreferredVectorAction(VT);
} }
MVT X86TargetLowering::getRegisterTypeForCallingConv(MVT VT) const {
if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())
return MVT::v32i8;
return TargetLowering::getRegisterTypeForCallingConv(VT);
}
MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context, MVT X86TargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
EVT VT) const { EVT VT) const {
if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI()) if (VT == MVT::v32i1 && Subtarget.hasAVX512() && !Subtarget.hasBWI())

2
lib/Target/X86/X86ISelLowering.h
View File

@ -1097,8 +1097,6 @@ namespace llvm {
/// Customize the preferred legalization strategy for certain types. /// Customize the preferred legalization strategy for certain types.
LegalizeTypeAction getPreferredVectorAction(EVT VT) const override; LegalizeTypeAction getPreferredVectorAction(EVT VT) const override;
MVT getRegisterTypeForCallingConv(MVT VT) const override;
MVT getRegisterTypeForCallingConv(LLVMContext &Context, MVT getRegisterTypeForCallingConv(LLVMContext &Context,
EVT VT) const override; EVT VT) const override;