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Add instruction encodings for ZEXT and SEXT.

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Previously these were marked with the wrong format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170327 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2012-12-17 13:20:37 +00:00
parent 5c531eb8b1
commit ff6114e872
2 changed files with 14 additions and 8 deletions
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16
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -764,20 +764,20 @@ def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
immBitp:$src2))]>;
def SEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
GRRegs:$src2))]>;
def SEXT_2r :
_F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"sext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
immBitp:$src2))]>;
def ZEXT_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src2, GRRegs:$src1),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
GRRegs:$src2))]>;
def ZEXT_2r :
_F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
"zext $dst, $src2",
[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
def ANDNOT_2r :
_F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),

6
test/MC/Disassembler/XCore/xcore.txt
View File

@ -132,3 +132,9 @@
# CHECK: setpsc res[r8], r2
0x28 0xc7
# CHECK: zext r3, r8
0x2c 0x47
# CHECK: sext r9, r1
0x45 0x37