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Disabled subregister copy coalescing during MachineCSE.

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This effectively backs out r197465 but leaves some of the general
fixes in place. Not all targets are ready to handle this feature. To
enable it, some infrastructure work is needed to better handle
register class constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197514 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-12-17 19:29:36 +00:00
parent de262fecd2
commit ff7e4b11b1
3 changed files with 17 additions and 6 deletions
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20
lib/CodeGen/MachineCSE.cpp
View File

@ -133,16 +133,26 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
continue;
if (DefMI->getOperand(0).getSubReg())
continue;
unsigned SrcSubReg = DefMI->getOperand(1).getSubReg();
// FIXME: We should trivially coalesce subregister copies to expose CSE
// opportunities on instructions with truncated operands (see
// cse-add-with-overflow.ll). This can be done here as follows:
// if (SrcSubReg)
// RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
// SrcSubReg);
// MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
//
// The 2-addr pass has been updated to handle coalesced subregs. However,
// some machine-specific code still can't handle it.
// To handle it properly we also need a way find a constrained subregister
// class given a super-reg class and subreg index.
if (DefMI->getOperand(1).getSubReg())
continue;
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
if (SrcSubReg)
RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
SrcSubReg);
if (!MRI->constrainRegClass(SrcReg, RC))
continue;
DEBUG(dbgs() << "Coalescing: " << *DefMI);
DEBUG(dbgs() << "*** to: " << *MI);
MO.substVirtReg(SrcReg, SrcSubReg, *TRI);
MO.setReg(SrcReg);
MRI->clearKillFlags(SrcReg);
DefMI->eraseFromParent();
++NumCoalesces;

2
test/CodeGen/X86/cmov.ll
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@ -42,7 +42,7 @@ declare void @bar(i64) nounwind
define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
; CHECK-LABEL: test3:
; CHECK: cmov{{n?}}el %[[R1:e..]], %[[R2:e..]]
; CHECK-NEXT: movl %[[R2]], %[[R2]]
; CHECK-NEXT: movl %[[R2]], %{{e..}}
%c = trunc i64 %a to i32
%d = trunc i64 %b to i32

1
test/CodeGen/X86/cse-add-with-overflow.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=generic | FileCheck %s
; XFAIL: *
; rdar:15661073 simple example of redundant adds
;
; MachineCSE should coalesce trivial subregister copies.