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TargetRegisterInfo: Make the concept of imprecise lane masks explicit
LaneMasks as given by getSubRegIndexLaneMask() have a limited number of of bits, so for targets with more than 31 disjunct subregister there may be cases where: getSubReg(Reg,A) does not overlap getSubReg(Reg,B) but we still have (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0. I had hoped to keep this an implementation detail of the tablegen but as my next commit shows we can avoid unnecessary imp-defs operands if we know that the lane masks in use are precise. This is in preparation to http://reviews.llvm.org/D10470. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239837 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -373,6 +373,19 @@ public:
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return SubRegIndexLaneMasks[SubIdx];
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}
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/// Returns true if the given lane mask is imprecise.
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///
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/// LaneMasks as given by getSubRegIndexLaneMask() have a limited number of
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/// bits, so for targets with more than 31 disjunct subregister indices there
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/// may be cases where:
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/// getSubReg(Reg,A) does not overlap getSubReg(Reg,B)
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/// but we still have
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/// (getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B)) != 0.
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/// This function returns true in those cases.
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static bool isImpreciseLaneMask(unsigned LaneMask) {
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return LaneMask & 0x80000000u;
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}
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/// The lane masks returned by getSubRegIndexLaneMask() above can only be
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/// used to determine if sub-registers overlap - they can't be used to
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/// determine if a set of sub-registers completely cover another
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@ -2633,7 +2633,8 @@ bool RegisterCoalescer::joinVirtRegs(CoalescerPair &CP) {
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// "overflow bit" 32. As a workaround we drop all subregister ranges
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// which means we loose some precision but are back to a well defined
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// state.
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assert((CP.getNewRC()->getLaneMask() & 0x80000000u)
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assert(TargetRegisterInfo::isImpreciseLaneMask(
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CP.getNewRC()->getLaneMask())
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&& "SubRange merge should only fail when merging into bit 32.");
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DEBUG(dbgs() << "\tSubrange join aborted!\n");
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LHS.clearSubRanges();
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