6 Commits

Author SHA1 Message Date
Michael Zolotukhin
9f101fa743 Remove redundant includes from utils/TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320632 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-13 21:31:13 +00:00
Alexander Shaposhnikov
18b16185df [tablegen] Avoid creating temporary strings
If a method / function returns a StringRef but the 
variable is of type const std::string& a temporary string is
created (StringRef has a cast operator to std::string),
which is a suboptimal behavior.

Differential revision: https://reviews.llvm.org/D34994

Test plan: make check-all


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@307195 91177308-0d34-0410-b5e6-96231b3b80d8
2017-07-05 20:14:54 +00:00
Craig Topper
2a129871cc [TableGen] Adapt more places to getValueAsString now returning a StringRef instead of a std::string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304347 91177308-0d34-0410-b5e6-96231b3b80d8
2017-05-31 21:12:46 +00:00
Benjamin Kramer
ae09a8743f [tblgen] Compare const char * with strcmp instead of creating StringRef.
Avoids a call to strlen on both strings which always reads the entire
string. strcmp can use early exit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276737 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-26 09:27:51 +00:00
Tim Northover
4d4806bd1c TableGen: avoid string copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274584 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-05 22:51:30 +00:00
Tim Northover
69ada669bc AArch64: TableGenerate system instruction operands.
The way the named arguments for various system instructions are handled at the
moment has a few problems:

  - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp
  - That weird Mapping class that I have no idea what I was on when I thought
    it was a good idea.
  - Searches are performed linearly through the entire list.
  - We print absolutely all registers in upper-case, even though some are
    canonically mixed case (SPSel for example).
  - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated
    to comments in our implementation, with a slightly opaque hex value
    indicating the canonical encoding LLVM will use.

This adds a new TableGen backend to produce efficiently searchable tables, and
switches AArch64 over to using that infrastructure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274576 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-05 21:23:04 +00:00