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68 Commits

Author SHA1 Message Date
Chris Lattner
84384546e2 Realize the constant pool & global addrs must always be ptr type 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24660 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-11 07:45:04 +00:00
Nate Begeman
28a6b02626 Add support for TargetConstantPool nodes to the dag isel emitter, and use 
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-10 02:36:00 +00:00
Evan Cheng
b612ff9569 Use SDTCisPtrTy type property for store address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24656 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-10 01:59:36 +00:00
Evan Cheng
b51a059b2c * Added X86 store patterns. 
* Added X86 dec patterns.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24654 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-10 00:48:20 +00:00
Chris Lattner
d8fe3b3272 Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load 
must be a pointer.  This removes a type check out of the code generated by
tblgen for load matching.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24650 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-09 22:58:42 +00:00
Evan Cheng
f20da7e1a7 Added support for ComplexPattern. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24638 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 04:28:48 +00:00
Chris Lattner
68bfd9c1e8 On some targets (e.g. X86), shift amounts are not the same as the value 
being shifted.  Don't assume they are.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24598 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-05 02:37:26 +00:00
Evan Cheng
f8ac814957 * Added instruction property hasCtrlDep for those which r/w control-flow 
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24586 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 08:13:17 +00:00
Chris Lattner
db40dc2d63 Add globaladdress and targetglobaladdress nodes for dag patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24389 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-17 07:20:15 +00:00
Duraid Madina
5966955445 add support for SELECT to TargetSelectionDAG.td, add support for 
selecting ints to IA64, and a few other ia64 bits and pieces


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24147 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-02 02:37:18 +00:00
Duraid Madina
e2fd9e2d9d add support for int->FP and FP->int ops, and add ia64 patterns for these 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24132 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-01 03:07:25 +00:00
Chris Lattner
1f426deade Add nodes for CondCodeSDNode and setcc, and add a bunch of pattern fragments 
to make it easy to use them.  This lets you write patterns like:

(set PRRC:$rd, (setne GPRC:$rS, imm:$SH))

and stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24009 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-26 17:00:25 +00:00
Chris Lattner
978982628a Add undef 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23990 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-25 21:03:14 +00:00
Chris Lattner
eae6d648da Use a literal to define ineg instead of immzero 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23851 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 23:30:37 +00:00
Andrew Lenharth
d684e1a64d add cttz and ctpop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23848 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-20 19:38:11 +00:00
Chris Lattner
444215dddc add the integer truncate/extension operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23733 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 06:40:20 +00:00
Chris Lattner
13664a6194 add a new SDTCisOpSmallerThanOp type constraint, and implement fround/fextend in terms of it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23726 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 04:55:10 +00:00
Chris Lattner
17f2cf05b3 Pull DAG ISel generation nodes out of the PowerPC backend to where they 
can be used by other targets.  For those targets that want to use it,
have at.  :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23680 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-10 06:00:30 +00:00