Commit Graph

4409 Commits

Author SHA1 Message Date
Dmitri Gribenko
9d227af8f7 Clarify comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164371 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21 15:26:34 +00:00
Micah Villmow
3e9b6db60f Add in new data types that are used by AMDIL/ANL among others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164261 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 22:47:07 +00:00
Owen Anderson
eb79b545fc Soften the pattern-can-never-match error in TableGen into a warning. This pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 22:15:06 +00:00
Craig Topper
8a312fb3aa Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 06:37:45 +00:00
Andrew Trick
3b8fb648c6 SchedMachineModel: compress the CPU's WriteLatencyTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 04:43:19 +00:00
Sean Silva
b2df610b44 Iterate deterministicaly over ClassInfo*'s
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164191 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 01:47:03 +00:00
Sean Silva
decfdf548b Iterate deterministically over register classes
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164190 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 01:47:01 +00:00
Sean Silva
90fee07298 Refactor Record* by-ID comparator to Record.h
This is a generally useful utility; there's no reason to have it hidden
in CodeGenDAGPatterns.cpp.

Also, rename it to fit the other comparators in Record.h

Review by Jakob.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164189 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-19 01:47:00 +00:00
Benjamin Kramer
30ce40e3f7 FileCheck: Fix off-by-one bug that made CHECK-NOT: ignore the next character after the colon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164165 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 20:51:39 +00:00
Craig Topper
3a36444366 Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164109 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 07:02:21 +00:00
Craig Topper
fee7f01d1e Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164108 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 06:10:45 +00:00
Andrew Trick
34aadd6334 Replaced ReInitMCSubtargetInfo with InitMCProcessor.
Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164105 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 05:33:15 +00:00
Andrew Trick
e076bb1e93 comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164097 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 04:03:30 +00:00
Andrew Trick
e3dbc98a4f TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:55:55 +00:00
Andrew Trick
4d2d1c49d7 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164095 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:41:43 +00:00
Andrew Trick
ee290ba35a TableGen subtarget emitter. Remove unnecessary header dependence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:32:57 +00:00
Andrew Trick
e127dfd0b1 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 03:18:56 +00:00
Craig Topper
b198f5c897 Mark asm matcher conversion table as const.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164088 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 01:41:49 +00:00
Craig Topper
be480ff607 Fix typo in comment. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164086 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-18 01:13:36 +00:00
Andrew Trick
e4095f95ac Backout the wrong subtarget emitter fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:14:15 +00:00
Andrew Trick
f23ddf54ea Fix release build after reverting
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164075 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:05:04 +00:00
Andrew Trick
e1b5328717 Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 23:00:42 +00:00
Andrew Trick
a2a47d1c50 InitMCProcessor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164066 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:12 +00:00
Andrew Trick
5d94082143 comment typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164064 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:04 +00:00
Andrew Trick
41be51b72c TableGen subtarget emitter. Use getSchedClassIdx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:19:01 +00:00
Andrew Trick
021ba269b2 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:58 +00:00
Andrew Trick
db7afac457 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:55 +00:00
Andrew Trick
544c88039f TableGen subtarget emitter. Format and emit data tables for the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:50 +00:00
Andrew Trick
52c3a1d654 TableGen subtarget emitter. Generate data tables for the new machine model.
Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:48 +00:00
Andrew Trick
40096d2693 TableGen subtarget emitter. Emit processor resources for the new machine model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164058 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:45 +00:00
Andrew Trick
bc4ff6e3cf TableGen subtarget parser: Add getProcResourcesIdx().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 22:18:43 +00:00
Jim Grosbach
9bb938c540 TableGen: Add initializer.
Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164041 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 18:00:53 +00:00
Axel Naumann
3780ad8b99 Fix a few vars that can end up being used without initialization.
The cases where no initialization happens should still be checked for logic flaws.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 14:20:57 +00:00
Michael Liao
efd841cdc5 Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164012 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-17 04:43:39 +00:00
Craig Topper
af8d66ce9a Add 'virtual' keywoards to output file for overridden functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164002 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-16 18:25:36 +00:00
Craig Topper
ef2340ef48 Add 'virtual' keywoards to output file for overridden functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-16 16:35:22 +00:00
Dmitri Gribenko
4e0ae44b3a Fix Doxygen issues: wrap code examples in \code and use \p to refer to
parameters.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 20:22:05 +00:00
Craig Topper
5974c31acb Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 01:22:42 +00:00
Andrew Trick
3cbd1786ac TableGen subtarget parser. Handle new machine model.
Collect processor resources from the subtarget defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 00:20:02 +00:00
Andrew Trick
5e613c260b TableGen subtarget parser. Handle new machine model.
Infer SchedClasses from variants defined by the target or subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 00:19:59 +00:00
Andrew Trick
48605c3406 TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-15 00:19:57 +00:00
Craig Topper
f4d78241ea Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163880 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 08:33:11 +00:00
Craig Topper
4e5babe4f3 Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163878 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 06:37:49 +00:00
Manman Ren
785a41d138 AsmWriterEmitter: OpInfo2 should be unsigned 16-bit.
Fix an issue in r163814.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 20:47:48 +00:00
Manman Ren
6579cf8df6 AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit to
48-bit if necessary, in order to reduce the generated code size.

We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel
AsmWriter and ARM AsmWriter.

This patch reduced the clang Release build size by 50k, running on a Mac Pro.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163814 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 17:43:46 +00:00
Dmitri Gribenko
2d9eb72178 Fix Doxygen issues:
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163790 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 12:34:29 +00:00
Craig Topper
76b29b518d Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163774 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-13 05:45:42 +00:00
Jim Grosbach
a562dc7228 TableGen: Convert an assert() to a proper diagnostic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163726 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 17:40:25 +00:00
Dmitri Gribenko
67c8978617 Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-12 16:59:47 +00:00
Owen Anderson
83c0eefa3b Improve tblgen code cleanliness: create an unknown_class, from which the unknown def inherits. Make tblgen check for that class, rather than checking for the def itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163664 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 23:47:08 +00:00
Owen Anderson
d2c699706c Compute a map from register names to registers, rather than scanning the list of registers every time we want to look up a register by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 23:32:17 +00:00
Jakob Stoklund Olesen
a6035773d8 Add TRI::getSubRegIndexLaneMask().
Sub-register lane masks are bitmasks that can be used to determine if
two sub-registers of a virtual register will overlap. For example, ARM's
ssub0 and ssub1 sub-register indices don't overlap each other, but both
overlap dsub0 and qsub0.

The lane masks will be accurate on most targets, but on targets that use
sub-register indexes in an irregular way, the masks may conservatively
report that two sub-register indices overlap when the eventually
allocated physregs don't.

Irregular register banks also mean that the bits in a lane mask can't be
mapped onto register units, but the concept is similar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 16:34:08 +00:00
Jakob Stoklund Olesen
de0250728b Clean the sub-reg index composition maps at emission.
Preserve the Composites map in the CodeGenSubRegIndex class so it can be
used to determine which sub-register indices can actually be composed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163629 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 16:34:05 +00:00
Jakob Stoklund Olesen
59f45e4610 Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163628 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 16:34:02 +00:00
Craig Topper
9e6dc8b9e7 Change unsigned to a uint16_t in static disassembler tables to reduce the table size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163594 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-11 04:19:21 +00:00
Evgeniy Stepanov
4fbaa509eb GTest on Android needs a custom tmpdir path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163501 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-10 10:32:29 +00:00
NAKAMURA Takumi
46b4b112d2 lit: Util.which(): Use os.path.isfile() instead of os.path.exists(), or it hits to the directory.
For example, which('loop-convert') returns 'loop-convert' when the directory 'loop-convert' exists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163469 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08 12:07:24 +00:00
Ted Kremenek
4f50517577 Revert "Add -exact-match option to FileCheck to allow clients to do exact matches without using regular expressions."
Turns out I did not need it after all.  If we find a use for it in the future, we
can resurrect it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163457 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-08 04:32:13 +00:00
Anshuman Dasgupta
3adf3b0ac0 Refactored DFA generator. Merged transition class into state class.
Patch by Ivan Llopard!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163424 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 21:35:43 +00:00
Ted Kremenek
2e578388ab Add -exact-match option to FileCheck to allow clients to do exact matches without using regular expressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163371 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 06:47:16 +00:00
Michael Liao
307525cd24 Re-work bit/bits value resolving in tblgen
- This patch is inspired by the failure of the following code snippet
  which is used to convert enumerable values into encoding bits to
  improve the readability of td files.

  class S<int s> {
    bits<2> V = !if(!eq(s, 8),  {0, 0},
                !if(!eq(s, 16), {0, 1},
                !if(!eq(s, 32), {1, 0},
                !if(!eq(s, 64), {1, 1}, {?, ?}))));
  }

  Later, PR8330 is found to report not exactly the same bug relevant
  issue to bit/bits values.

- Instead of resolving bit/bits values separately through
  resolveBitReference(), this patch adds getBit() for all Inits and
  resolves bit value by resolving plus getting the specified bit. This
  unifies the resolving of bit with other values and removes redundant
  logic for resolving bit only. In addition,
  BitsInit::resolveReferences() is optimized to take advantage of this
  origanization by resolving VarBitInit's variable reference first and
  then getting bits from it.

- The type interference in '!if' operator is revised to support possible
  combinations of int and bits/bit in MHS and RHS.

- As there may be illegal assignments from integer value to bit, says
  assign 2 to a bit, but we only check this during instantiation in some
  cases, e.g.

  bit V = !if(!eq(x, 17), 0, 2);

  Verbose diagnostic message is generated when invalid value is
  resolveed to help locating the error.

- PR8330 is fixed as well.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163360 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 23:32:48 +00:00
Tom Stellard
6d3d765653 Tablegen: Add OperandWithDefaultOps Operand type
This Operand type takes a default argument, and is initialized to
this value if it does not appear in a patter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163315 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 14:15:52 +00:00
Nadav Rotem
c05d30601c Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 09:17:37 +00:00
Roman Divacky
98eb98b0f2 Constify subtarget info properly so that we dont cast away the const in
the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 21:43:57 +00:00
Chad Rosier
5d637d7e93 Fix function name per coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163187 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 01:15:43 +00:00
Chad Rosier
90e11f8c95 Fix function name per coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163186 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-05 01:02:38 +00:00
Chad Rosier
4e2132e7ae [ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. This
implementation does not co-exist well with how the sideeffect and alignstack
attributes are handled.  The reverts r161641.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163174 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 22:29:45 +00:00
David Blaikie
7a9572f8af [LIT] Add a clang_tools_extra_site_cfg to match the various other site_cfg.
This doesn't seem ideal, perhaps we could just keep the llvm_site_cfg and have
other config (clang and clang-tools-extra) derive their site_cfg from that.

Suggestions/complaints/ideas welcome.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163171 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 22:09:04 +00:00
Evgeniy Stepanov
68d92bdcc9 Fix Android build of gtest and lib/Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163131 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-04 09:14:45 +00:00
Chad Rosier
2dc88d94c3 [ms-inline asm] Make comment more verbose and add an assert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163125 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 20:37:01 +00:00
Chad Rosier
2cc97def74 [ms-inline asm] Asm operands can map to one or more MCOperands. Therefore, add
the NumMCOperands argument to the GetMCInstOperandNum() function that is set
to the number of MCOperands this asm operand mapped to.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 20:31:23 +00:00
Chad Rosier
038f3e3127 [ms-inline asm] Add an interface to the GetMCInstOperandNum() function in the
MCTargetAsmParser class.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163122 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 18:47:45 +00:00
Chad Rosier
ad2d3e637a Remove extraneous return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163119 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 17:39:57 +00:00
Chad Rosier
87d910efc6 [ms-inline asm] Return the MCOperandNum instead of passing a reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163118 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 17:33:50 +00:00
Chad Rosier
c4d2560a20 Removed unused argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163104 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 03:16:09 +00:00
Chad Rosier
3a86e13962 [ms-inline asm] Expose the Kind and Opcode variables from the
MatchInstructionImpl() function.

These values are used by the ConvertToMCInst() function to index into the
ConversionTable.  The values are also needed to call the GetMCInstOperandNum()
function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-03 02:06:46 +00:00
Chad Rosier
756d2cc2f7 Remove an unused argument. The MCInst opcode is set in the ConvertToMCInst()
function nowadays.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 22:12:31 +00:00
Craig Topper
bf4043768c Add support for converting llvm.fma to fma4 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 15:40:30 +00:00
Chad Rosier
359956dc1b With the fix in r162954/162955 every cvt function returns true. Thus, have
the ConvertToMCInst() return void, rather then a bool.  Update all the cvt
functions as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162961 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-31 00:03:31 +00:00
Chad Rosier
389536cf44 Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 21:47:00 +00:00
Chad Rosier
04508c6cb7 Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 21:46:00 +00:00
Chad Rosier
0bad086d6d Hoist a check to eliminate obvious mismatches as early as possible. Also, fix
an 80-column violation in the generated code.  No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162944 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 21:43:05 +00:00
Chad Rosier
62316fa00a [ms-inline asm] Add a new function, GetMCInstOperandNum, to the
AsmMatcherEmitter.  This function maps inline assembly operands to MCInst
operands.

For example, '__asm mov j, eax' is represented by the follow MCInst:

<MCInst 1460 <MCOperand Reg:0> <MCOperand Imm:1> <MCOperand Reg:0> 
             <MCOperand Expr:(j)> <MCOperand Reg:0> <MCOperand Reg:43>>

The first 5 MCInst operands are a result of j matching as a memory operand
consisting of a BaseReg (Reg:0), MemScale (Imm:1), MemIndexReg(Reg:0), 
Expr (Expr:(j), and a MemSegReg (Reg:0).  The 6th MCInst operand represents
the eax register (Reg:43).

This translation is necessary to determine the Input and Output Exprs.  If a
single asm operand maps to multiple MCInst operands, the index of the first
MCInst operand is returned.  Ideally, it would return the operand we really
care out (i.e., the Expr:(j) in this case), but I haven't found an easy way
of doing this yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162920 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-30 17:59:25 +00:00
Andrew Trick
2b70dfaaeb Fix a nondeterminism in the ARM assembler.
Adding arbitrary records to ARM.td would break
basic-arm-instructions.s because selection of nop vs mov r0,r0 was
ambiguous (this will be tested by a subsequent addition to ARM.td).
An imperfect but sensible fix is to give precedence to match rules
that have more constraints.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162824 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-29 03:52:57 +00:00
Jakob Stoklund Olesen
325907d086 Check all patterns for missing instruction flags.
Both single-instruction and multi-instruction patterns can be checked
for missing mayLoad / mayStore, and hasSideEffects flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162734 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-28 03:26:49 +00:00
Richard Smith
1144af3c9b Fix integer undefined behavior due to signed left shift overflow in LLVM.
Reviewed offline by chandlerc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 23:29:28 +00:00
Jakob Stoklund Olesen
4ad27eda29 Infer instruction properties from single-instruction patterns.
Previously, instructions without a primary patterns wouldn't get their
properties inferred. Now, we use all single-instruction patterns for
inference, including 'def : Pat<>' instances.

This causes a lot of instruction flags to change.

- Many instructions no longer have the UnmodeledSideEffects flag because
  their flags are now inferred from a pattern.

- Instructions with intrinsics will get a mayStore flag if they already
  have UnmodeledSideEffects and a mayLoad flag if they already have
  mayStore. This is because intrinsics properties are linear.

- Instructions with atomic_load patterns get a mayStore flag because
  atomic loads can't be reordered. The correct workaround is to create
  pseudo-instructions instead of using normal loads. PR13693.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162614 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 22:46:53 +00:00
Jakob Stoklund Olesen
aaaecfce70 Stop inferring isVariadic from instruction patterns.
Instructions are now only marked as variadic if they use variable_ops in
their ins list.

A variadic SDNode is typically used for call nodes that have the call
arguments as operands.

A variadic MachineInstr can actually encode a variable number of
operands, for example ARM's stm/ldm instructions. A call instruction
does not have to be variadic. The call argument registers are added as
implicit operands.

This change remove the MCID::Variadic flags from most call and return
instructions, allowing us to better verify their operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162599 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 21:08:09 +00:00
Jakob Stoklund Olesen
91f8dc9bae Verify explicit instruction properties when they can be inferred.
It is now allowed to explicitly set hasSideEffects, mayStore, and
mayLoad on instructions with patterns.

Verify that the patterns are consistent with the explicit flags.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162569 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 17:08:41 +00:00
Jakob Stoklund Olesen
912519a72e Heed guessInstructionProperties, and stop warning on redundant flags.
Emit TableGen errors if guessInstructionProperties is 0 and
instruction properties can't be inferred from patterns.

Allow explicit instruction properties even when they can be inferred.

This patch doesn't change the TableGen output. Redundant properties
are not yet verified because the tree has errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162516 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-24 00:31:16 +00:00
Jakob Stoklund Olesen
c1f10fd5b9 Tristate mayLoad, mayStore, and hasSideEffects.
Keep track of the set/unset state of these bits along with their
true/false values, but treat '?' as '0' for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162461 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:34:46 +00:00
Jakob Stoklund Olesen
f104bf65b9 Add CodeGenTarget::guessInstructionProperties.
Currently, TableGen just guesses instruction properties when it can't
infer them form patterns.

This adds a guessInstructionProperties flag to the instruction set
definition that will be used to disable guessing. The flag is intended
as a migration aid. It will be removed again when no more targets need
their properties guessed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162460 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 19:34:41 +00:00
Dmitri Gribenko
a00b80b04c Fix a bunch of -Wdocumentation warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162446 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-23 16:54:08 +00:00
Jakob Stoklund Olesen
376a8a773e Print out the location of expanded multiclass defs in TableGen errors.
When reporting an error for a defm, we would previously only report the
location of the outer defm, which is not always where the error is.

Now we also print the location of the expanded multiclass defs:

lib/Target/X86/X86InstrSSE.td:2902:12: error: foo
  defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
             ^
lib/Target/X86/X86InstrSSE.td:2801:11: note: instantiated from multiclass
  defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
            ^
lib/Target/X86/X86InstrSSE.td:194:5: note: instantiated from multiclass
    def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
        ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162409 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 23:33:58 +00:00
Jim Grosbach
c8f267f669 TblGen: Make asm-matcher ConvertToMCInst() table driven.
No change in interface or functionality. Purely under-the-hood
details of the generated function that change.

The X86 assembly parser is reduced in size by over 15% and ARM by
over 10%.

No performance change by my measurements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162337 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-22 01:06:23 +00:00
Chad Rosier
4c1d2baa7c Formatting. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162292 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-21 17:22:47 +00:00
Akira Hatanaka
72e9b6aeb4 Add stub methods for mips assembly matcher.
Patch by Vladimir Medic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162124 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 20:16:42 +00:00
Craig Topper
8cd9eaef01 Declare some for loop indices inside the for loop statement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162085 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 05:42:16 +00:00
Craig Topper
c056483fc6 Fix up indentation of outputted decode function for readability.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 05:16:15 +00:00
NAKAMURA Takumi
c797f2e9c7 lit: Show actually created count of threads. The incorrect threads count is printed if the number of tests are less than the number of default threads.
Thanks to Vinson Lee, reported in PR13620.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162078 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-17 04:15:41 +00:00
Jakob Stoklund Olesen
f2c64ef519 Add an MCID::Select flag and TII hooks for optimizing selects.
Select instructions pick one of two virtual registers based on a
condition, like x86 cmov. On targets like ARM that support predication,
selects can sometimes be eliminated by predicating the instruction
defining one of the operands.

Teach PeepholeOptimizer to recognize select instructions, and ask the
target to optimize them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162059 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-16 23:11:47 +00:00
Jakob Stoklund Olesen
d024a20bf7 Add a CoveringSubRegIndices field to SubRegIndex records.
This can be used to tell TableGen to use a specific SubRegIndex instead
of synthesizing one when discovering all sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15 20:15:48 +00:00
Jakob Stoklund Olesen
c97eda2c9e Make synthesized sub-register indexes available in the target namespace.
TableGen sometimes synthesizes missing sub-register indexes. Emit these
indexes as enumerators in the target namespace along with the
user-defined ones.

Also take this opportunity to stop creating new Record objects for
synthetic indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161964 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15 18:00:55 +00:00
Benjamin Kramer
95d235ddb6 Fix a const violation in the generated disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161940 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-15 10:26:44 +00:00
Jim Grosbach
fc1a161d76 Switch the fixed-length disassembler to be table-driven.
Refactor the TableGen'erated fixed length disassemblmer to use a
table-driven state machine rather than a massive set of nested
switch() statements.

As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more
quickly and generates a smaller end result. For a Release+Asserts build on
a 16GB 3.4GHz i7 iMac w/ SSD:

Time to compile at -O2 (averaged w/ hot caches):
  Previous: 35.5s
  New:       8.9s

TEXT size:
  Previous: 447,251
  New:      297,661

Builds in 25% of the time previously required and generates code 66% of
the size.

Execution time of the disassembler is only slightly slower (7% disassembling
10 million ARM instructions, 19.6s vs 21.0s). The new implementation has
not yet been tuned, however, so the performance should almost certainly
be recoverable should it become a concern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-14 19:06:05 +00:00
Joerg Sonnenberger
78cab947cf Add some missing includes for the build against stdcxx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161657 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 10:53:56 +00:00
Bob Wilson
ec175ff270 Use the final .version number for LLVM_MINOR_VERSION in Apple llvmCore builds.
We've switched to a 3-component version numbering scheme for Apple releases,
and with this scheme, the final number is the one most relevant for setting
LLVM_MINOR_VERSION.  <rdar://problem/12071459>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161645 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 00:25:30 +00:00
Chad Rosier
249d670dd0 [ms-inline asm] Add a new Inline Asm Non-Standard Dialect attribute.
This new attribute is intended to be used by the backend to determine how
the inline asm string should be parsed/printed. This patch adds the 
ia_nsdialect attribute and also adds a test case to ensure the IR is
correctly parsed, but there is no functional change at this time.

The standard dialect is assumed to be AT&T.  Therefore, this attribute
should only be added to MS-style inline assembly statements, which use
the Intel dialect.  If we ever support more dialects we'll need to
add additional state to the attribute.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161641 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-10 00:00:22 +00:00
Andrew Trick
d43b5c97cf Added MispredictPenalty to SchedMachineModel.
This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-08 02:44:16 +00:00
Bill Wendling
087642f863 Remove extraneous ';'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-04 10:31:40 +00:00
Richard Trieu
7b07d69958 Remove redundant '== true' after a comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161223 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 23:22:39 +00:00
Michael J. Spencer
1de266be13 [yaml2obj] Fix build. Apparently I've gotten too familiar with C++11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161206 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 19:36:30 +00:00
Michael J. Spencer
a915f247f7 Add yaml2obj. A utility to convert YAML to binaries.
yaml2obj takes a textual description of an object file in YAML format
and outputs the binary equivalent. This greatly simplifies writing
tests that take binary object files as input.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161205 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-02 19:16:56 +00:00
Craig Topper
5a2c607153 Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161101 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-01 07:39:18 +00:00
Michael J. Spencer
d77ce4a8e9 [obj2yaml] Print the Relocations header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161082 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 22:04:08 +00:00
Ted Kremenek
521ed460e9 Use regex instead of special casing clang and llvm libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161065 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 18:23:44 +00:00
Craig Topper
19dbe2f5f0 Use uint8_t to store the InstructionContext table. Saves 768 bytes of static data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 06:15:39 +00:00
Craig Topper
de9e333e18 Tidy up. Move for loop index declarations into for statements. Use unsigned instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 06:02:05 +00:00
Craig Topper
e08789f5e2 Tidy up function argument formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161032 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 05:42:02 +00:00
Craig Topper
a31359a529 Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161031 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 05:28:41 +00:00
Craig Topper
9840009ff8 Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161030 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-31 05:27:01 +00:00
Craig Topper
49d86c9eb9 Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30 06:48:11 +00:00
Craig Topper
95c929f45c Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160950 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30 06:27:19 +00:00
Craig Topper
24fd0ddf31 Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160949 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30 05:39:34 +00:00
Craig Topper
50c5c8275e Simplify code that filtered certain instructions in two different ways. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160948 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30 05:10:05 +00:00
Craig Topper
87a9ece154 Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30 04:53:00 +00:00
Craig Topper
e6c97ffb0d Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-30 04:48:12 +00:00
Craig Topper
f553587a4f Clean up includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160852 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-27 06:44:02 +00:00
Jakob Stoklund Olesen
0371cd8b1c Eliminate the large XXXSubRegTable constant arrays.
These tables were indexed by [register][subreg index] which made them,
very large and sparse.

Replace them with lists of sub-register indexes that match the existing
lists of sub-registers. MCRI::getSubReg() becomes a very short linear
search, like getSubRegIndex() already was.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-27 00:10:51 +00:00
Jakob Stoklund Olesen
2ca6b3c374 Remove support for 'CompositeIndices' and sub-register cycles.
Now that the weird X86 sub_ss and sub_sd sub-register indexes are gone,
there is no longer a need for the CompositeIndices construct in .td
files. Sub-register index composition can be specified on the
SubRegIndex itself using the ComposedOf field.

Also enforce unique names for sub-registers in TableGen. The same
sub-register cannot be available with multiple sub-register indexes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26 23:39:50 +00:00
Craig Topper
7f76cb6666 Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160775 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-26 07:48:28 +00:00
Jakob Stoklund Olesen
303c909d5b Differentially encode all MC register lists.
This simplifies MCRegisterInfo and shrinks the target descriptions a bit
more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160758 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-25 21:41:37 +00:00
Eric Christopher
581a739226 Fix a "Bad fd number" error on some platforms due to a less portable
redirection in the system call.

Patch by Andy Gibbs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160644 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23 20:54:17 +00:00
Sylvestre Ledru
c8e41c5917 Fix a typo (the the => the)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160621 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-23 08:51:15 +00:00
Daniel Dunbar
b1a4642796 lit: Use close_fds=True on UNIX, to avoid file descriptor pollution of
subprocesses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-20 18:29:34 +00:00
Richard Trieu
76f63aef56 Move around some enum elements so that lastMRM corrects gets assigned 56, which
is one more that MRM_DF which is 55.  Previously, it held value 45, the same
as MRM_D0.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160465 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18 23:04:22 +00:00
Jim Grosbach
b8d17643a5 TblGen: Tweak to pretty-print DAGISel.inc a bit better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160463 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18 22:41:03 +00:00
Craig Topper
75dc33a60b Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-18 04:11:12 +00:00
Jim Grosbach
d3e31218ef TableGen: Pattern<> references to null_frag are a nop.
A standalone pattern defined in a multiclass expansion should handle
null_frag references just like patterns on instructions. Follow-up to
r160333.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160384 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 18:39:36 +00:00
Jim Grosbach
ac915b48d8 TableGen: Allow conditional instruction pattern in multiclass.
Define a 'null_frag' SDPatternOperator node, which if referenced in an
instruction Pattern, results in the pattern being collapsed to be as-if
'[]' had been specified instead. This allows supporting a multiclass
definition where some instaniations have ISel patterns associated and
others do not.

For example,
multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> {
  def _x : myI<(outs rc:), (ins rc:), []>;
  def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>;
}

defm foo : myMulti<GRa, not>;
defm bar : myMulti<GRb>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 00:47:06 +00:00
Owen Anderson
b885dc8d39 Defer checking for registers in the MC AsmMatcher until the after user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 23:20:09 +00:00
Jim Grosbach
151d81d1e7 TableGen: Assembly matcher 'insufficient operands' diagnostic.
Make sure the tblgen'erated asm matcher correctly returns numoperands+1
as the ErrorInfo when the problem was that there weren't enough operands
specified.

rdar://9142751

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160144 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12 21:37:20 +00:00
Craig Topper
5aba78bd80 Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-12 06:52:41 +00:00
Andrew Trick
cb94192ff0 Machine model: allow itineraries to be shared by different processor models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-09 20:43:03 +00:00
Andrew Trick
2661b411cc I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159891 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 04:00:00 +00:00
Andrew Trick
06495cd7f2 whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159890 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 03:59:51 +00:00
Andrew Trick
a11a6287a5 Tweak spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159889 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-07 03:59:48 +00:00
Chandler Carruth
1f7ebddd5f Revert r159528 which taught lit's builtin shell test runner about the
'|&' bash syntax. We have lots of users with a bash on their system
which doesn't support this syntax, and as bash is still significantly
faster, we should support them.

The test suite has already been updated to cope with this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159580 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 20:43:21 +00:00
Chandler Carruth
506bb19d10 Fix the C++11 build. I hate narrowing conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159543 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 18:28:34 +00:00
Andrew Trick
218ee74a01 Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary."
Reapplies r159406 with minor cleanup. The regressions appear to have been spurious.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159541 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-02 18:10:42 +00:00