Commit Graph

12722 Commits

Author SHA1 Message Date
Xin Tong 773ad8be84 [ThinLTO] Keep non-prevailing (linkonce|weak)_odr symbols live
Summary:
If we have a symbol with (linkonce|weak)_odr linkage, we do not want
to dead strip it even it is not prevailing.

IR level (linkonce|weak)_odr symbol can become non-prevailing when we mix
ELF objects and IR objects where the (linkonce|weak)_odr symbol in the ELF
object is prevailing and the ones in the IR objects are not. Stripping
them will prevent us from doing optimizations with them.

By not dead stripping them, We will convert these symbols to
available_externally linkage as a result of non-prevailing and eventually
dropping them after inlining.

I modified cache-prevailing.ll to use linkonce linkage as it is
testing whether cache prevailing bit is effective or not, not
we should treat linkonce_odr alive or not

Reviewers: tejohnson, pcc

Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D52893

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343970 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-08 15:12:48 +00:00
Ewan Crawford 3948aa1d82 [InstCombine] Fix incongruous GEP type addrspace
Currently running the @insertelem_after_gep function below through the InstCombine pass with opt produces invalid IR.

Input:
```
define void @insertelem_after_gep(<16 x i32>* %t0) {
   %t1 = bitcast <16 x i32>* %t0 to [16 x i32]*
   %t2 = addrspacecast [16 x i32]* %t1 to [16 x i32] addrspace(3)*
   %t3 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* %t2, i64 0, i64 0
   %t4 = insertelement <16 x i32 addrspace(3)*> undef, i32 addrspace(3)* %t3, i32 0
   call void @extern_vec_pointers_func(<16 x i32 addrspace(3)*> %t4)
   ret void
}
```

Output:

```
define void @insertelem_after_gep(<16 x i32>* %t0) {
  %t3 = getelementptr inbounds <16 x i32>, <16 x i32>* %t0, i64 0, i64 0
  %t4 = insertelement <16 x i32 addrspace(3)*> undef, i32 addrspace(3)* %t3, i32 0
  call void @my_extern_func(<16 x i32 addrspace(3)*> %t4)
  ret void
}
```

Which although causes no complaints when produced, isn't valid IR as the insertelement use of the %t3 GEP expects an address space.

```
opt: /tmp/bad.ll:52:73: error: '%t3' defined with type 'i32*' but expected 'i32 addrspace(3)*'
  %t4 = insertelement <16 x i32 addrspace(3)*> undef, i32 addrspace(3)* %t3, i32 0
```

I've fixed this by adding an addrspacecast after the GEP in the InstCombine pass, and including a check for this type mismatch to the verifier.

Reviewers: spatel, lebedev.ri
Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52294


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343956 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-08 08:40:45 +00:00
Max Kazantsev eb3fd4c932 [LV] Do not create SCEVs on broken IR in emitTransformedIndex. PR39160
At the point when we perform `emitTransformedIndex`, we have a broken IR (in
particular, we have Phis for which not every incoming value is properly set). On
such IR, it is illegal to create SCEV expressions, because their internal
simplification process may try to prove some predicates and break when it
stumbles across some broken IR.

The only purpose of using SCEV in this particular place is attempt to simplify
the generated code slightly. It seems that the result isn't worth it, because
some trivial cases (like addition of zero and multiplication by 1) can be
handled separately if needed, but more generally InstCombine is able to achieve
the goals we want to achieve by using SCEV.

This patch fixes a functional crash described in PR39160, and as side-effect it
also generates a bit smarter code in some simple cases. It also may cause some
optimality loss (i.e. we will now generate `mul` by power of `2` instead of
shift etc), but there is nothing what InstCombine could not handle later. In
case of dire need, we can support more trivial cases just in place.

Note that this patch only fixes one particular case of the general problem that
LV misuses SCEV, attempting to create SCEVs or prove predicates on invalid IR.
The general solution, however, seems complex enough.

Differential Revision: https://reviews.llvm.org/D52881
Reviewed By: fhahn, hsaito


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343954 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-08 05:46:29 +00:00
Sanjay Patel d28883e615 [InstSimplify] add vector test for fneg+fdiv; NFC
This should be fixed with D52934.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343936 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-07 14:46:33 +00:00
Dorit Nuzman 2e1904606d [IAI,LV] Avoid creating interleave-groups for predicated accesse
This patch fixes PR39099.

When strided loads are predicated, each of them will form an interleaved-group
(with gaps). However, subsequent stages of vectorization (planning and
transformation) assume that if a load is part of an Interleave-Group it is not
predicated, resulting in wrong code - unmasked wide loads are created.

The Interleaving Analysis does take care not to have conditional interleave
groups of size > 1, but until we extend the planning and transformation stages
to support masked-interleave-groups we should also avoid having them for
size == 1.

Reviewers: Ayal, hsaito, dcaballe, fhahn

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D52682



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343931 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-07 06:57:25 +00:00
Sanjay Patel f2f6f77ac4 [InstCombine] drop poison flags in SimplifyVectorDemandedElts
We established the (unfortunately complicated) rules for UB/poison
propagation with vector ops in:
D48893
D48987
D49047

It's clear from the affected tests that we are potentially creating 
poison where none existed before the transforms. For add/sub/mul,
the answer is simple: just drop the flags because the extra undef
vector lanes are generally more valuable for analysis and codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343819 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-04 21:36:50 +00:00
Sanjay Patel 62aab8af14 [InstCombine] allow bitcast to/from FP for vector insert/extract transform
This is a follow-up to rL343482 / D52439.
This was a pattern that initially caused the commit to be reverted because
the transform requires a bitcast as shown here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343794 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-04 16:25:05 +00:00
Sanjay Patel 44cfbc7d13 [InstCombine] allow SimplifyDemandedVectorElts to work with FP binops
We're a long way from D50992 and D51553, but this is where we have to start.
We weren't back-propagating undefs into binop constant values for anything but
add/sub/mul/and/or/xor. 

This is likely because we have to be careful about not introducing UB/poison 
with div/rem/shift. But I suspect we already are getting the poison part wrong 
for add/sub/mul (although it may not be possible to expose the bug currently
because we use SimplifyDemandedVectorElts from a limited set of opcodes).
See the discussion/implementation from D48987 and D49047.

This patch just enables functionality for FP ops because those do not have 
UB/poison potential.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343727 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-03 21:44:59 +00:00
Sanjay Patel 748b49e389 [InstCombine] add tests for binop undef-into-constant propagation; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343714 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-03 20:35:25 +00:00
Aditya Kumar f7ae0df654 Add support for new pass manager
Modified the testcases to use both pass managers
Use single commandline flag for both pass managers.

Differential Revision: https://reviews.llvm.org/D52708
Reviewers: sebpop, tejohnson, brzycki, SirishP
Reviewed By: tejohnson, brzycki

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343662 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-03 05:55:20 +00:00
Sanjay Patel 20ec0569b5 [InstCombine] add icmp+logic tests with commuted ops; NFC
The transform in question is located in foldICmpAndConstConst(),
but as shown here, it doesn't work if operands are commuted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343646 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 22:53:37 +00:00
Sanjay Patel 1b9f2a9da5 [InstCombine] add tests with undef elements; NFC
See discussion in D52747.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343595 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 15:00:56 +00:00
Sanjay Patel cbe63a8c2b [InstCombine] add more insert/extract vector tests with FP types; NFC
These are candidates for the same fold that was implemented in
D52439, but FP types require bitcasting (and that changes the
extra uses profitability calculation).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343587 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:34:05 +00:00
David Green cf1b18658c [InstCombine] Fold ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - A
This is an attempt to get out of a local-minimum that instcombine currently
gets stuck in. We essentially combine two optimisations at once, ~a - ~b = b-a
and min(~a, ~b) = ~max(a, b), only doing the transform if the result is at
least neutral. This involves using IsFreeToInvert, which has been expanded a
little to include selects that can be easily inverted.

This is trying to fix PR35875, using the ideas from Sanjay. It is a large
improvement to one of our rgb to cmy kernels.

Differential Revision: https://reviews.llvm.org/D52177


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343569 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:48:34 +00:00
David Green abe8e0a65f [InstCombine] Tests for ~A - Min/Max(~A, O) -> Max/Min(A, ~O) - A. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343561 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:06:49 +00:00
Matt Arsenault b3a02e1925 AMDGPU: Expand atomicrmw nand in IR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343559 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 03:50:56 +00:00
Sanjay Patel e467ad47ea [InstCombine] add inverse test for vector trunc canonical form; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343529 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 20:25:49 +00:00
Sanjay Patel aba2e4f005 [InstCombine] regenerate test checks; NFC
These files used an old version of the script.
We regex more now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343527 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 20:22:28 +00:00
Jesper Antonsson 6b99c7f259 [InstCombine] Handle vector compares in foldGEPIcmp(), take 2
Summary:
This is a continuation of the fix for PR34627 "InstCombine assertion at vector gep/icmp folding". (I just realized bugpoint had fuzzed the original test for me, so I had fixed another trigger of the same assert in adjacent code in InstCombine.)

This patch avoids optimizing an icmp (to look only at the base pointers) when the resulting icmp would have a different type.

The patch adds a testcase and also cleans up and shrinks the pre-existing test for the adjacent assert trigger.

Reviewers: lebedev.ri, majnemer, spatel

Reviewed By: lebedev.ri

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52494

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343486 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 14:59:25 +00:00
Sanjay Patel f7cc35b1ce [InstCombine] try to convert vector insert+extract to trunc; 2nd try
This was originally committed at rL343407, but reverted at 
rL343458 because it crashed trying to handle a case where
the destination type is FP. This version of the patch adds
a check for that possibility. Tests added at rL343480.

Original commit message:

This transform is requested for the backend in:
https://bugs.llvm.org/show_bug.cgi?id=39016
...but I figured it was worth doing in IR too, and it's probably
easier to implement here, so that's this patch.

In the simplest case, we are just truncating a scalar value. If the
extract index doesn't correspond to the LSBs of the scalar, then we
have to shift-right before the truncate. Endian-ness makes this tricky,
but hopefully the ASCII-art helps visualize the transform.

Differential Revision: https://reviews.llvm.org/D52439


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343482 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 14:40:00 +00:00
Sanjay Patel 0b13e12729 [InstCombine] add more insert-extract tests for D52439; NFC
The first attempt at this transform:
rL343407
...was reverted:
rL343458
...because it did not handle the case where we bitcast to FP. 
The patch was already limited to avoid the case where we
bitcast from FP, but we might want to transform that too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343480 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 14:29:09 +00:00
Hans Wennborg f7f9563cf4 Revert r343407 "[InstCombine] try to convert vector insert+extract to trunc"
This caused Chromium builds to fail with "Illegal Trunc" assertion.
See https://crbug.com/890723 for repro.

> This transform is requested for the backend in:
> https://bugs.llvm.org/show_bug.cgi?id=39016
> ...but I figured it was worth doing in IR too, and it's probably
> easier to implement here, so that's this patch.
>
> In the simplest case, we are just truncating a scalar value. If the
> extract index doesn't correspond to the LSBs of the scalar, then we
> have to shift-right before the truncate. Endian-ness makes this tricky,
> but hopefully the ASCII-art helps visualize the transform.
>
> Differential Revision: https://reviews.llvm.org/D52439

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343458 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 12:07:45 +00:00
Sanjay Patel 8594ae0860 [InstCombine] try to convert vector insert+extract to trunc
This transform is requested for the backend in:
https://bugs.llvm.org/show_bug.cgi?id=39016
...but I figured it was worth doing in IR too, and it's probably 
easier to implement here, so that's this patch.

In the simplest case, we are just truncating a scalar value. If the 
extract index doesn't correspond to the LSBs of the scalar, then we 
have to shift-right before the truncate. Endian-ness makes this tricky, 
but hopefully the ASCII-art helps visualize the transform.

Differential Revision: https://reviews.llvm.org/D52439


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343407 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 14:34:01 +00:00
Sanjay Patel 22030c13ce [InstCombine] allow lengthening of insertelement to eliminate shuffles
As noted in post-commit comments for D52548, the limitation on 
increasing vector length can be applied by opcode.
As a first step, this patch only allows insertelement to be
widened because that has no logical downsides for IR and has 
little risk of pessimizing codegen.

This may cause PR39132 to go into hiding during a full compile,
but that bug is not fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343406 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 13:50:42 +00:00
Sanjay Patel 5bf17aa03a [InstCombine] add test for vector widening of insertelements; NFC
The test shows a potential overreach with the fix from D52548.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343378 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 15:01:45 +00:00
Sanjay Patel 331a5ec713 [InstCombine] don't propagate wider shufflevector arguments to predecessors
InstCombine would propagate shufflevector insts that had wider output vectors onto 
predecessors, which would sometimes push undef's onto the divisor of a div/rem and 
result in bad codegen.

I've fixed this by just banning propagating shufflevector back if the result of 
the shufflevector is wider than the input vectors.

Patch by: @sheredom (Neil Henning)

Differential Revision: https://reviews.llvm.org/D52548



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343329 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 15:24:41 +00:00
Sanjay Patel 5c806329ca [InstCombine] adjust shuffle undef propagation tests; NFC
These are the updated baseline tests for D52548 -
I'm putting the tests next to the tests where the transform 
functions as expected, so we can see the intended/unintended
consequences.

Patch by: @sheredom (Neil Henning)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343328 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 15:20:06 +00:00
Craig Topper 6752904763 [ScalarizeMaskedMemIntrin] Use MinAlign to calculate alignment for the scalar load/stores to handle element types that are byte-sized but not powers of 2.
This pass doesn't handle non-byte sized types correctly at all, but at least we can make byte sized types work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343294 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 03:35:37 +00:00
Craig Topper bcbf6bc493 [ScalarizeMaskedMemIntrin] Fix the alignment calculation for the scalar stores of a masked store expansion.
It should be the minimum of the original alignment and the scalar size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343284 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 01:06:13 +00:00
Craig Topper dee8e5347f [ScalarizeMaskedMemIntrin] Add test cases for masked store expansion. Increase alignment of one of the masked load test cases.
The masked store alignment is being miscalculated, but masked load is correct.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343283 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 01:06:09 +00:00
Craig Topper 2122d188d1 [ScalarizeMaskedMemIntrin] When expanding masked gathers, start with the passthru vector and insert the new load results into it.
Previously we started with undef and did a final merge with the passthru at the end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343273 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 21:28:59 +00:00
Craig Topper c670432bdd [ScalarizeMaskedMemIntrin] Add some IR only test cases for masked gather expansion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343272 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 21:28:55 +00:00
Craig Topper 4f95400123 [ScalarizeMaskedMemIntrin] When expanding masked loads, start with the passthru value and insert each conditional load result over their element.
Previously we started with undef and did one final merge at the end with a select.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343271 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 21:28:52 +00:00
Craig Topper 4b75b6ed93 [ScalarizeMaskedMemIntrin] Handle the case where the mask is an all zero vector.
This shouldn't really happen in practice I hope, but we tried to handle other constant cases. We missed this one because we checked for ConstantVector without realizing that zero becomes ConstantAggregateZero instead.

So instead just check for Constant and use getAggregateElement which will do the dirty work for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343270 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 21:28:46 +00:00
Craig Topper fe9a6b988a [ScalarizeMaskedMemIntrin] Add dedicated IR only tests for masked load expansion so I can begin making modifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343269 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 21:28:43 +00:00
Sanjay Patel 94a9f57861 [InstCombine] Without infinites, fold (C / X) < 0.0 --> (X < 0)
When C is not zero and infinites are not allowed (C / X) > 0 is a sign
test. Depending on the sign of C, the predicate must be swapped.

E.g.:
  foo(double X) {
    if ((-2.0 / X) <= 0) ...
  }
 =>
  foo(double X) {
    if (X >= 0) ...
  }

Patch by: @marels (Martin Elshuber)

Differential Revision: https://reviews.llvm.org/D51942


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343228 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 15:59:24 +00:00
Sanjay Patel fa611d49bb [InstCombine] add tests for FP sign-bit cmp optimization with fdiv; NFC
These are baseline tests for D51942.
Patch by: @marels (Martin Elshuber)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343222 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 14:24:29 +00:00
Nicola Zaghen c335565127 [InstCombine] Add new tests in preparation for a combine of icmp (mul nsw/nuw X, C2), C
Proof for the future optimisations are here:
- eq/neq: https://rise4fun.com/Alive/9PBA
- sgt/ugt: https://rise4fun.com/Alive/58yr
- slt/ult: https://rise4fun.com/Alive/VCQ

Differential Revision: https://reviews.llvm.org/D51625



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343190 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-27 10:08:38 +00:00
Sanjay Patel cc53e50232 [InstCombine] add tests that show undef propagation failures from D52548; NFC
Differential Revision: https://reviews.llvm.org/D52556


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343140 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 20:30:47 +00:00
Florian Hahn 08733c9b06 [LoopInterchange] Preserve LCSSA.
This patch extends LoopInterchange to move LCSSA to the right place
after interchanging. This is required for LoopInterchange to become a
function pass.

An alternative to the manual moving of the PHIs, we could also re-form
the LCSSA phis for a set of interchanged loops, but that's more
expensive.

Reviewers: efriedma, mcrosier, davide

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D52154



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343132 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 19:34:25 +00:00
Sanjay Patel 31b94bfe45 [InstCombine] add tests for vector insert/extract; NFC
Preliminary step for D52439.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343128 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 17:57:38 +00:00
David Green ae073c99a4 [CodeGen] Enable tail calls for functions with NonNull attributes.
Adding NonNull as attributes to returned pointers has the unfortunate side
effect of disabling tail calls. This patch ignores the NonNull attribute when
we decide whether to tail merge, in the same way that we ignore the NoAlias
attribute, as it has no affect on the call sequence.

Differential Revision: https://reviews.llvm.org/D52238


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343091 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 10:46:18 +00:00
Vyacheslav Zakharin 5088aa8e41 Remove LoopID metadata from the branch instruction
that follows the peeled iterations.

Differential Revision: https://reviews.llvm.org/D52176



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343054 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-26 01:03:21 +00:00
Sanjay Patel 3b27ccc7ea [InstCombine] add fneg variation of shuffle-binop fold; NFC
If the fsub in this pattern was replaced by an actual fneg
instruction, we would need to add a fold to recognize that
because fneg would not be a binop.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343041 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-25 22:48:58 +00:00
Anna Thomas edafc389f1 [LV][LAA] Vectorize loop invariant values stored into loop invariant address
Summary:
We are overly conservative in loop vectorizer with respect to stores to loop
invariant addresses.
More details in https://bugs.llvm.org/show_bug.cgi?id=38546
This is the first part of the fix where we start with vectorizing loop invariant
values to loop invariant addresses.

This also includes changes to ORE for stores to invariant address.

Reviewers: anemet, Ayal, mkuper, mssimpso

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343028 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-25 20:57:20 +00:00
Teresa Johnson 0d4dfd227e [ThinLTO] Efficiency fix for writing type id records in per-module indexes
Summary:
In D49565/r337503, the type id record writing was fixed so that only
referenced type ids were emitted into each per-module index for ThinLTO
distributed builds. However, this still left an efficiency issue: each
per-module index checked all type ids for membership in the referenced
set, yielding O(M*N) performance (M indexes and N type ids).

Change the TypeIdMap in the summary to be indexed by GUID, to facilitate
correlating with type identifier GUIDs referenced in the function
summary TypeIdInfo structures. This allowed simplifying other
places where a map from type id GUID to type id map entry was previously
being used to aid this correlation.

Also fix AsmWriter code to handle the rare case of type id GUID
collision.

For a large internal application, this reduced the thin link time by
almost 15%.

Reviewers: pcc, vitalybuka

Subscribers: mehdi_amini, inglorion, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51330

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343021 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-25 20:14:40 +00:00
Sanjay Patel d66c208522 [InstCombine] narrow binops on concatenated vectors (PR33026)
The motivating case from:
https://bugs.llvm.org/show_bug.cgi?id=33026
...has no shuffles now. This kind of pattern may occur during
vectorization when targets have lumpy ISAs like SSE/AVX.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342988 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-25 15:57:37 +00:00
David Green 50bc8f679d [LoopUnroll] Add check to Latch's terminator in UnrollRuntimeLoopRemainder
In this patch, I'm adding an extra check to the Latch's terminator in llvm::UnrollRuntimeLoopRemainder,
similar to how it is already done in the llvm::UnrollLoop.

The compiler would crash if this function is called with a malformed loop.

Patch by Rodrigo Caetano Rocha!

Differential Revision: https://reviews.llvm.org/D51486


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342958 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-25 10:08:47 +00:00
Christy Lee 2d8135ffd9 Re-submitting changes in D51550 because it failed to patch.
Reviewers: javed.absar, trentxintong, courbet

Reviewed By: trentxintong

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52433

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342919 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-24 20:47:12 +00:00
Christy Lee 512e6852ef Reland r342494 after fixing LIT checks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@342907 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-24 17:26:30 +00:00