Commit Graph

27162 Commits

Author SHA1 Message Date
Guillaume Chatelet 237f2f2909 [Alignment][NFC] Remove LoadInst::setAlignment(unsigned)
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet, jdoerfert

Subscribers: hiraditya, asbirlea, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D68142

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373195 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-30 09:37:05 +00:00
Hans Wennborg 4d6b6c6b00 NFC changes to SelectionDAGBuilder::visitBitTestHeader(), preparing for PR43129
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373191 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-30 08:47:53 +00:00
Roger Ferrer Ibanez ca6e7338d6 [TargetLowering] Simplify expansion of S{ADD,SUB}O
ISD::SADDO uses the suggested sequence described in the section §2.4 of
the RISCV Spec v2.2. ISD::SSUBO uses the dual approach but checking for
(non-zero) positive.

Differential Revision: https://reviews.llvm.org/D47927

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373187 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-30 07:58:50 +00:00
Amara Emerson 4818f426ab Add an operand to memory intrinsics to denote the "tail" marker.
We need to propagate this information from the IR in order to be able to safely
do tail call optimizations on the intrinsics during legalization. Assuming
it's safe to do tail call opt without checking for the marker isn't safe because
the mem libcall may use allocas from the caller.

This adds an extra immediate operand to the end of the intrinsics and fixes the
legalizer to handle it.

Differential Revision: https://reviews.llvm.org/D68151

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373140 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-28 05:33:21 +00:00
Jakub Kuderski 9d38ddb712 Revert [Dominators][CodeGen] Clean up MachineDominators
This reverts r373101 (git commit 72c57ec3e6b320c31274dadb888dc16772b8e7b6)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373117 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-27 19:33:39 +00:00
Jakub Kuderski 49b18f846e [Dominators][CodeGen] Clean up MachineDominators
Summary: This is a cleanup patch for MachineDominatorTree. It would be an NFC, except for replacing custom DomTree verification with the generic one.

Reviewers: tstellar, tpr, nhaehnle, arsenm, NutshellySima, grosser, hliao

Reviewed By: arsenm

Subscribers: wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67976

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373101 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-27 17:25:39 +00:00
Djordje Todorovic bc913bfd01 [DebugInfo] Exclude memory location values as parameter entry values
Abandon describing of loaded values due to safety concerns. Loaded
values are described as derefed memory location at caller point.
At callee we can unintentionally change that memory location which
would lead to different entry being printed value before and after
the memory location clobbering. This problem is described in
llvm.org/PR43343.

Patch by Nikola Prica

Differential Revision: https://reviews.llvm.org/D67717

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373089 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-27 13:52:43 +00:00
Jesper Antonsson fd525cdd72 [CodeGenPrepare] Mend "avoid crashing from replacing a phi twice" fix.
Summary:
An erroneously negated if-statement by an earlier (March 2019) bugfix left phi replacement/simplification under optimizeMemoryInst()  in CodeGenPrepare largely inactivated. The error was found when csmith found that the same assert as in the original bug report could still be triggered in a different way. This patch fixes the bugfix. The original bug was:
 https://bugs.llvm.org/show_bug.cgi?id=41052
... and the previous fix was D59358.

Reviewers: aprantl, skatkov

Reviewed By: skatkov

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67838

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373084 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-27 13:01:37 +00:00
Guillaume Chatelet 71864c0be5 [Alignment][NFC] Remove unneeded llvm:: scoping on Align types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373081 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-27 12:54:21 +00:00
Hans Wennborg e15a2ad07a Revert r372893 "[CodeGen] Replace -max-jump-table-size with -max-jump-table-targets"
This caused severe compile-time regressions, see PR43455.

> Modern processors predict the targets of an indirect branch regardless of
> the size of any jump table used to glean its target address.  Moreover,
> branch predictors typically use resources limited by the number of actual
> targets that occur at run time.
>
> This patch changes the semantics of the option `-max-jump-table-size` to limit
> the number of different targets instead of the number of entries in a jump
> table.  Thus, it is now renamed to `-max-jump-table-targets`.
>
> Before, when `-max-jump-table-size` was specified, it could happen that
> cluster jump tables could have targets used repeatedly, but each one was
> counted and typically resulted in tables with the same number of entries.
> With this patch, when specifying `-max-jump-table-targets`, tables may have
> different lengths, since the number of unique targets is counted towards the
> limit, but the number of unique targets in tables is the same, but for the
> last one containing the balance of targets.
>
> Differential revision: https://reviews.llvm.org/D60295

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373060 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-27 09:54:26 +00:00
Changpeng Fang b07705b701 Remove the AliasAnalysis argument in function areMemAccessesTriviallyDisjoint
Reviewers:
  arsenm

Differential Revision:
  https://reviews.llvm.org/D58360

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373024 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-26 22:53:44 +00:00
Xiangling Liao c58a5d49af [AIX]Emit function descriptor csect in assembly
This patch emits the function descriptor csect for functions with definitions
under both 32-bit/64-bit mode on AIX.

Differential Revision: https://reviews.llvm.org/D66724

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373009 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-26 19:38:32 +00:00
Mikael Holmen 91fdf5127f [IfConversion] Disallow TBB == FBB for valid triangles
Summary:
Previously the case

     EBB
     | \_
     |  |
     | TBB
     |  /
     FBB

was treated as a valid triangle also when TBB and FBB was the same basic
block. This could then lead to an invalid CFG when we removed the edge
from EBB to TBB, since that meant we would also remove the edge from EBB
to FBB.

Since TBB == FBB is quite a degenerated case of a triangle, we now
don't treat it as a valid triangle anymore, and thus we will avoid the
trouble with updating the CFG.

Reviewers: efriedma, dmgreen, kparzysz

Reviewed By: efriedma

Subscribers: bjope, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67832

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372943 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-26 06:35:55 +00:00
Thomas Raoux 3a2a144e7e [TargetLowering] Make allowsMemoryAccess methode virtual.
Rename old function to explicitly show that it cares only about alignment.
The new allowsMemoryAccess call the function related to alignment by default
and can be overridden by target to inform whether the memory access is legal or
not.

Differential Revision: https://reviews.llvm.org/D67121

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372935 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-26 00:16:01 +00:00
Jessica Paquette 126b679a29 [AArch64][GlobalISel] Choose CCAssignFns per-argument for tail call lowering
When checking for tail call eligibility, we should use the correct CCAssignFn
for each argument, rather than just checking if the caller/callee is varargs or
not.

This is important for tail call lowering with varargs. If we don't check it,
then basically any varargs callee with parameters cannot be tail called on
Darwin, for one thing. If the parameters are all guaranteed to be in registers,
this should be entirely safe.

On top of that, not checking for this could potentially make it so that we have
the wrong stack offsets when checking for tail call eligibility.

Also refactor some of the stuff for CCAssignFnForCall and pull it out into a
helper function.

Update call-translator-tail-call.ll to show that we can now correctly tail call
on Darwin. Also add two extra tail call checks. The first verifies that we still
respect the caller's stack size, and the second verifies that we still don't
tail call when a varargs function has a memory argument.

Differential Revision: https://reviews.llvm.org/D67939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372897 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 16:45:35 +00:00
Evandro Menezes bd5ddbcfeb [CodeGen] Replace -max-jump-table-size with -max-jump-table-targets
Modern processors predict the targets of an indirect branch regardless of
the size of any jump table used to glean its target address.  Moreover,
branch predictors typically use resources limited by the number of actual
targets that occur at run time.

This patch changes the semantics of the option `-max-jump-table-size` to limit
the number of different targets instead of the number of entries in a jump
table.  Thus, it is now renamed to `-max-jump-table-targets`.

Before, when `-max-jump-table-size` was specified, it could happen that
cluster jump tables could have targets used repeatedly, but each one was
counted and typically resulted in tables with the same number of entries.
With this patch, when specifying `-max-jump-table-targets`, tables may have
different lengths, since the number of unique targets is counted towards the
limit, but the number of unique targets in tables is the same, but for the
last one containing the balance of targets.

Differential revision: https://reviews.llvm.org/D60295

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372893 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 16:10:20 +00:00
Sanjay Patel d7ca0d78e9 [DAGCombiner] add one-use restriction to vector transform with cheap extract
We might be able to do better on the example in the test,
but in general, we should not scalarize a splatted vector
binop if there are other uses of the binop. Otherwise, we
can end up with code as we had - a scalar op that is
redundant with a vector op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372886 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 15:08:33 +00:00
Simon Pilgrim e8d798abaa [TargetInstrInfo] Let findCommutedOpIndices take const MachineInstr&
Neither the base implementation of findCommutedOpIndices nor any in-tree target modifies the instruction passed in and there is no reason why they would in the future.

Committed on behalf of @hvdijk (Harald van Dijk)

Differential Revision: https://reviews.llvm.org/D66138

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372882 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 14:55:57 +00:00
Jakub Kuderski a06891a3ca [Dominators][AMDGPU] Don't use virtual exit node in findNearestCommonDominator. Cleanup MachinePostDominators.
Summary:
This patch fixes a bug that originated from passing a virtual exit block (nullptr) to `MachinePostDominatorTee::findNearestCommonDominator` and resulted in assertion failures inside its callee. It also applies a small cleanup to the class.

The patch introduces a new function in PDT that given a list of `MachineBasicBlock`s finds their NCD. The new overload of `findNearestCommonDominator` handles virtual root correctly.

Note that similar handling of virtual root nodes is not necessary in (forward) `DominatorTree`s, as right now they don't use virtual roots.

Reviewers: tstellar, tpr, nhaehnle, arsenm, NutshellySima, grosser, hliao

Reviewed By: hliao

Subscribers: hliao, kzhuravl, jvesely, wdng, yaxunl, dstuttard, t-tye, hiraditya, llvm-commits

Tags: #amdgpu, #llvm

Differential Revision: https://reviews.llvm.org/D67974

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372874 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 14:04:36 +00:00
Sanjay Patel 9dcc14cb65 Revert [IR] allow fast-math-flags on phi of FP values
This reverts r372866 (git commit dec03223a97af0e4dfcb23da55c0f7f8c9b62d00)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372868 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 13:29:09 +00:00
Sanjay Patel 5d102992ac [IR] allow fast-math-flags on phi of FP values
The changes here are based on the corresponding diffs for allowing FMF on 'select':
D61917

As discussed there, we want to have fast-math-flags be a property of an FP value
because the alternative (having them on things like fcmp) leads to logical
inconsistency such as:
https://bugs.llvm.org/show_bug.cgi?id=38086

The earlier patch for select made almost no practical difference because most
unoptimized conditional code begins life as a phi (based on what I see in clang).
Similarly, I don't expect this patch to do much on its own either because
SimplifyCFG promptly drops the flags when converting to select on a minimal
example like:
https://bugs.llvm.org/show_bug.cgi?id=39535

But once we have this plumbing in place, we should be able to wire up the FMF
propagation and start solving cases like that.

The change to RecurrenceDescriptor::AddReductionVar() is required to prevent a
regression in a LoopVectorize test. We are intersecting the FMF of any
FPMathOperator there, so if a phi is not properly annotated, new math
instructions may not be either. Once we fix the propagation in SimplifyCFG, it
may be safe to remove that hack.

Differential Revision: https://reviews.llvm.org/D67564

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372866 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 13:14:12 +00:00
Simon Pilgrim 7324e2c791 [DAG] Pull out minimum shift value calc into a helper function. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372856 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-25 12:28:56 +00:00
Simon Pilgrim 8eabc0f8e4 AggressiveAntiDepBreaker - silence static analyzer null dereference warning. NFCI.
Assert that we've found the critical path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372759 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-24 13:57:51 +00:00
Ilya Biryukov 8fa9e1c8a5 Revert r372333: [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (PR42863)
Reason: this caused severe compile time regressions in JAX.
See email thread  of original revision on llvm-commits for details:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20190923/697042.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372756 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-24 13:48:02 +00:00
Simon Pilgrim 8a02de4582 [ModuloSchedule] KernelRewriter::rewrite - silence static analyzer dyn_cast<> null dereference warning. NFCI.
Assert that we've found the start of the MI schedule list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372723 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-24 10:58:42 +00:00
Simon Pilgrim 73485f3e48 lowerObjCCall - silence static analyzer dyn_cast<CallInst> null dereference warnings. NFCI.
The static analyzer is warning about a potential null dereference, but we should be able to use cast<CallInst> directly and if not assert will fire for us.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372720 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-24 10:46:30 +00:00
Pavel Labath d93e5a30d0 MCRegisterInfo: Merge getLLVMRegNum and getLLVMRegNumFromEH
Summary:
The functions different in two ways:
- getLLVMRegNum could return both "eh" and "other" dwarf register
  numbers, while getLLVMRegNumFromEH only returned the "eh" number.
- getLLVMRegNum asserted if the register was not found, while the second
  function returned -1.

The second distinction was pretty important, but it was very hard to
infer that from the function name. Aditionally, for the use case of
dumping dwarf expressions, we needed a function which can work with both
kinds of number, but does not assert.

This patch solves both of these issues by merging the two functions into
one, returning an Optional<unsigned> value. While the same thing could
be achieved by adding an "IsEH" argument to the (renamed)
getLLVMRegNumFromEH function, it seemed better to avoid the confusion of
two functions and put the choice of asserting into the hands of the
caller -- if he checks the Optional value, he can safely process
"untrusted" input, and if he blindly dereferences the Optional, he gets
the assertion.

I've updated all call sites to the new API, choosing between the two
options according to the function they were calling originally, except
that I've updated the usage in DWARFExpression.cpp to use the "safe"
method instead, and added a test case which would have previously
triggered an assertion failure when processing (incorrect?) dwarf
expressions.

Reviewers: dsanders, arsenm, JDevlieghere

Subscribers: wdng, aprantl, javed.absar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67154

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372710 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-24 09:31:02 +00:00
Amara Emerson 36e6c6c028 [GlobalISel][IRTranslator] Fix switch table lowering to use signed LE not unsigned.
We were miscompiling switch value comparisons with the wrong signedness, which
shows up when we have things like switch case values with i1 types, which end up
being legalized incorrectly.

Fixes PR43383

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372675 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-24 00:09:23 +00:00
Sanjay Patel e61b10cb03 [BreakFalseDeps] ignore function with minsize attribute
This came up in the x86-specific:
https://bugs.llvm.org/show_bug.cgi?id=43239
...but it is a general problem for the BreakFalseDeps pass.
Dependencies may be broken by adding some other instruction,
so that should be avoided if the overall goal is to minimize size.

Differential Revision: https://reviews.llvm.org/D67363

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372628 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-23 17:01:01 +00:00
Guillaume Chatelet c1f79bc5bd [Alignment][NFC] DataLayout migration to llvm::Align
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: jholewinski, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67914

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372596 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-23 12:41:36 +00:00
Simon Pilgrim 6ec2ed215c Localizer - fix "variable used but never read" analyzer warning. NFCI.
Simplify the code by separating the modification of the Changed variable from returning it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372583 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-23 11:38:10 +00:00
Simon Pilgrim fed25f49be TargetInstrInfo::getStackSlotRange - fix "variable used but never read" analyzer warning. NFCI.
We don't need to divide the BitSize local variable at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372582 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-23 11:36:24 +00:00
Simon Pilgrim 5e951112cb CriticalAntiDepBreaker - Assert that we've found the bottom of the critical path. NFCI.
Silences static analyzer null dereference warnings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372577 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-23 10:42:47 +00:00
Craig Topper 3592730a61 [X86][SelectionDAGBuilder] Move the hack for handling MMX shift by i32 intrinsics into the X86 backend.
This intrinsics should be shift by immediate, but gcc allows any
i32 scalar and clang needs to match that. So we try to detect the
non-constant case and move the data from an integer register to an
MMX register.

Previously this was done by creating a v2i32 build_vector and
bitcast in SelectionDAGBuilder. This had to be done early since
v2i32 isn't a legal type. The bitcast+build_vector would be DAG
combined to X86ISD::MMX_MOVW2D which isel will turn into a
GPR->MMX MOVD.

This commit just moves the whole thing to lowering and emits
the X86ISD::MMX_MOVW2D directly to avoid the illegal type. The
test changes just seem to be due to nodes being linearized in a
different order.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372535 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-23 01:05:33 +00:00
Simon Pilgrim 4432ce935e [SelectionDAG] computeKnownBits/ComputeNumSignBits - cleanup demanded/unknown paths. NFCI.
Merge the calls, just adjust the demandedelts if we have a valid extract_subvector constant index, else demand all elts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372521 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-22 18:47:12 +00:00
James Molloy 6d4a6cde0a [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCount
Recommit: fix asan errors.

The way MachinePipeliner uses these target hooks is stateful - we reduce trip
count by one per call to reduceLoopCount. It's a little overfit for hardware
loops, where we don't have to worry about stitching a loop induction variable
across prologs and epilogs (the induction variable is implicit).

This patch introduces a new API:

  /// Analyze loop L, which must be a single-basic-block loop, and if the
  /// conditions can be understood enough produce a PipelinerLoopInfo object.
  virtual std::unique_ptr<PipelinerLoopInfo>
  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const;

The return value is expected to be an implementation of the abstract class:

  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
  /// implementations to query attributes of the loop being pipelined.
  class PipelinerLoopInfo {
  public:
    virtual ~PipelinerLoopInfo();
    /// Return true if the given instruction should not be pipelined and should
    /// be ignored. An example could be a loop comparison, or induction variable
    /// update with no users being pipelined.
    virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;

    /// Create a condition to determine if the trip count of the loop is greater
    /// than TC.
    ///
    /// If the trip count is statically known to be greater than TC, return
    /// true. If the trip count is statically known to be not greater than TC,
    /// return false. Otherwise return nullopt and fill out Cond with the test
    /// condition.
    virtual Optional<bool>
    createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
                                 SmallVectorImpl<MachineOperand> &Cond) = 0;

    /// Modify the loop such that the trip count is
    /// OriginalTC + TripCountAdjust.
    virtual void adjustTripCount(int TripCountAdjust) = 0;

    /// Called when the loop's preheader has been modified to NewPreheader.
    virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;

    /// Called when the loop is being removed.
    virtual void disposed() = 0;
  };

The Pipeliner (ModuloSchedule.cpp) can use this object to modify the loop while
allowing the target to hold its own state across all calls. This API, in
particular the disjunction of creating a trip count check condition and
adjusting the loop, improves the code quality in ModuloSchedule.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372463 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-21 08:19:41 +00:00
Amara Emerson bb0fdfda6f [GlobalISel] Defer setting HasCalls on MachineFrameInfo to selection time.
We currently always set the HasCalls on MFI during translation and legalization if
we're handling a call or legalizing to a libcall. However, if that call is later
optimized to a tail call then we don't need the flag. The flag being set to true
causes frame lowering to always save and restore FP/LR, which adds unnecessary code.

This change does the same thing as SelectionDAG and ports over some code that scans
instructions after selection, using TargetInstrInfo to determine if target opcodes
are known calls.

Code size geomean improvements on CTMark:
 -O0 : 0.1%
 -Os : 0.3%

Differential Revision: https://reviews.llvm.org/D67868

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372443 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 23:52:07 +00:00
Mitch Phillips e7563c448e Revert "[MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCount"
This commit broke the ASan buildbot. See comments in rL372376 for more
information.

This reverts commit 15e27b0b6d9d51362fad85dbe95ac5b3fadf0a06.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372425 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 20:25:16 +00:00
Craig Topper 483a636ee0 [SelectionDAG][Mips][Sparc] Don't allow SimplifyDemandedBits to constant fold TargetConstant nodes to a Constant.
Summary:
After the switch in SimplifyDemandedBits, it tries to create a
constant when possible. If the original node is a TargetConstant
the default in the switch will call computeKnownBits on the
TargetConstant which will succeed. This results in the
TargetConstant becoming a Constant. But TargetConstant exists to
avoid being changed.

I've fixed the two cases that relied on this in tree by explicitly
making the nodes constant instead of target constant. The Sparc
case is an old bug. The Mips case was recently introduced now that
ImmArg on intrinsics gets turned into a TargetConstant when the
SelectionDAG is created. I've removed the ImmArg since it lowers
to generic code.

Reviewers: arsenm, RKSimon, spatel

Subscribers: jyknight, sdardis, wdng, arichardson, hiraditya, fedor.sergeev, jrtc27, atanasyan, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67802

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372409 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 16:49:51 +00:00
Krzysztof Parzyszek 392a95b5fe [MVT] Add v256i1 to MachineValueType
This type can show up when lowering some HVX vector code on Hexagon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372403 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 15:19:20 +00:00
David Stenberg 22b465abb4 Add a missing space in a MIR parser error message
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372398 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 14:41:41 +00:00
David Tellenbach 0b85459856 [FastISel] Fix insertion of unconditional branches during FastISel
The insertion of an unconditional branch during FastISel can differ depending on
building with or without debug information. This happens because FastISel::fastEmitBranch
emits an unconditional branch depending on the size of the current basic block
without distinguishing between debug and non-debug instructions.

This patch fixes this issue by ignoring debug instructions when getting the size
of the basic block.

Reviewers: aprantl

Reviewed By: aprantl

Subscribers: ormris, aprantl, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67703

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372389 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 13:22:59 +00:00
James Molloy d2ee0056e8 [MachinePipeliner] Improve the TargetInstrInfo API analyzeLoop/reduceLoopCount
The way MachinePipeliner uses these target hooks is stateful - we reduce trip
count by one per call to reduceLoopCount. It's a little overfit for hardware
loops, where we don't have to worry about stitching a loop induction variable
across prologs and epilogs (the induction variable is implicit).

This patch introduces a new API:

  /// Analyze loop L, which must be a single-basic-block loop, and if the
  /// conditions can be understood enough produce a PipelinerLoopInfo object.
  virtual std::unique_ptr<PipelinerLoopInfo>
  analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const;

The return value is expected to be an implementation of the abstract class:

  /// Object returned by analyzeLoopForPipelining. Allows software pipelining
  /// implementations to query attributes of the loop being pipelined.
  class PipelinerLoopInfo {
  public:
    virtual ~PipelinerLoopInfo();
    /// Return true if the given instruction should not be pipelined and should
    /// be ignored. An example could be a loop comparison, or induction variable
    /// update with no users being pipelined.
    virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0;

    /// Create a condition to determine if the trip count of the loop is greater
    /// than TC.
    ///
    /// If the trip count is statically known to be greater than TC, return
    /// true. If the trip count is statically known to be not greater than TC,
    /// return false. Otherwise return nullopt and fill out Cond with the test
    /// condition.
    virtual Optional<bool>
    createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB,
                                 SmallVectorImpl<MachineOperand> &Cond) = 0;

    /// Modify the loop such that the trip count is
    /// OriginalTC + TripCountAdjust.
    virtual void adjustTripCount(int TripCountAdjust) = 0;

    /// Called when the loop's preheader has been modified to NewPreheader.
    virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0;

    /// Called when the loop is being removed.
    virtual void disposed() = 0;
  };

The Pipeliner (ModuloSchedule.cpp) can use this object to modify the loop while
allowing the target to hold its own state across all calls. This API, in
particular the disjunction of creating a trip count check condition and
adjusting the loop, improves the code quality in ModuloSchedule.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372376 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 08:57:46 +00:00
Matt Arsenault c62b24f070 MachineScheduler: Fix missing dependency with multiple subreg defs
If an instruction had multiple subregister defs, and one of them was
undef, this would improperly conclude all other lanes are
killed. There could still be other defs of those read-undef lanes in
other operands. This would improperly remove register uses from
CurrentVRegUses, so the visitation of later operands would not find
the necessary register dependency. This would also mean this would
fail or not depending on how different subregister def operands were
ordered.

On an undef subregister def, scan the instruction for other
subregister defs and avoid killing those.

This possibly should be deferring removing anything from
CurrentVRegUses until the entire instruction has been processed
instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372362 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-20 00:09:15 +00:00
Matt Arsenault db7d9c2217 Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
This reverts r372314, reapplying r372285 and the commits which depend
on it (r372286-r372293, and r372296-r372297)

This was missing one switch to getTargetConstant in an untested case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372338 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-19 16:26:14 +00:00
Simon Pilgrim 0c28ee7b1c [DAG][X86] Convert isNegatibleForFree/GetNegatedExpression to a target hook (PR42863)
This patch converts the DAGCombine isNegatibleForFree/GetNegatedExpression into overridable TLI hooks and includes a demonstration X86 implementation.

The intention is to let us extend existing FNEG combines to work more generally with negatible float ops, allowing it work with target specific combines and opcodes (e.g. X86's FMA variants).

Unlike the SimplifyDemandedBits, we can't just handle target nodes through a Target callback, we need to do this as an override to allow targets to handle generic opcodes as well. This does mean that the target implementations has to duplicate some checks (recursion depth etc.).

I've only begun to replace X86's FNEG handling here, handling FMADDSUB/FMSUBADD negation and some low impact codegen changes (some FMA negatation propagation). We can build on this in future patches.

Differential Revision: https://reviews.llvm.org/D67557

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372333 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-19 15:02:47 +00:00
Amaury Sechet ccb1e74959 [DAGCombiner] Add node to the worklist in topological order in scalarizeExtractedVectorLoad
Summary: As per title.

Reviewers: craig.topper, efriedma, RKSimon, lebedev.ri

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66661

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372327 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-19 14:22:11 +00:00
Simon Pilgrim 23be00fbf3 [DAG] Add SelectionDAG::MaxRecursionDepth constant
As commented on D67557 we have a lot of uses of depth checks all using magic numbers.

This patch adds the SelectionDAG::MaxRecursionDepth constant and moves over some general cases to use this explicitly.

Differential Revision: https://reviews.llvm.org/D67711

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372315 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-19 12:58:43 +00:00
Hans Wennborg 0c2a34c502 Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"
This broke the Chromium build, causing it to fail with e.g.

  fatal error: error in backend: Cannot select: t362: v4i32 = X86ISD::VSHLI t392, Constant:i8<15>

See llvm-commits thread of r372285 for details.

This also reverts r372286, r372287, r372288, r372289, r372290, r372291,
r372292, r372293, r372296, and r372297, which seemed to depend on the
main commit.

> Encode them directly as an imm argument to G_INTRINSIC*.
>
> Since now intrinsics can now define what parameters are required to be
> immediates, avoid using registers for them. Intrinsics could
> potentially want a constant that isn't a legal register type. Also,
> since G_CONSTANT is subject to CSE and legalization, transforms could
> potentially obscure the value (and create extra work for the
> selector). The register bank of a G_CONSTANT is also meaningful, so
> this could throw off future folding and legalization logic for AMDGPU.
>
> This will be much more convenient to work with than needing to call
> getConstantVRegVal and checking if it may have failed for every
> constant intrinsic parameter. AMDGPU has quite a lot of intrinsics wth
> immarg operands, many of which need inspection during lowering. Having
> to find the value in a register is going to add a lot of boilerplate
> and waste compile time.
>
> SelectionDAG has always provided TargetConstant for constants which
> should not be legalized or materialized in a register. The distinction
> between Constant and TargetConstant was somewhat fuzzy, and there was
> no automatic way to force usage of TargetConstant for certain
> intrinsic parameters. They were both ultimately ConstantSDNode, and it
> was inconsistently used. It was quite easy to mis-select an
> instruction requiring an immediate. For SelectionDAG, start emitting
> TargetConstant for these arguments, and using timm to match them.
>
> Most of the work here is to cleanup target handling of constants. Some
> targets process intrinsics through intermediate custom nodes, which
> need to preserve TargetConstant usage to match the intrinsic
> expectation. Pattern inputs now need to distinguish whether a constant
> is merely compatible with an operand or whether it is mandatory.
>
> The GlobalISelEmitter needs to treat timm as a special case of a leaf
> node, simlar to MachineBasicBlock operands. This should also enable
> handling of patterns for some G_* instructions with immediates, like
> G_FENCE or G_EXTRACT.
>
> This does include a workaround for a crash in GlobalISelEmitter when
> ARM tries to uses "imm" in an output with a "timm" pattern source.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372314 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-19 12:33:07 +00:00
Matt Arsenault 34f46973b8 MachineScheduler: Fix assert from not checking subregs
The assert would fail if there was a dead def of a subregister if
there was a previous use of a different subregister.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372287 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-19 02:14:12 +00:00