Commit Graph

59474 Commits

Author SHA1 Message Date
George Rimar ca483bfba2 [obj2yaml][yaml2obj] - Add support of parsing/dumping of the .gnu.version_r section.
The section is described here:
https://refspecs.linuxfoundation.org/LSB_1.3.0/gLSB/gLSB/symverrqmts.html

Patch just teaches obj2yaml/yaml2obj to dump and parse such sections.

We did the finalization of string tables very late,
and I had to move the logic to make it a bit earlier.
That was needed in this patch since .gnu.version_r adds strings to .dynstr.
This might also be useful for implementing other special sections.

Everything else changed in this patch seems to be straightforward.

Differential revision: https://reviews.llvm.org/D58119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354328 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-19 14:03:14 +00:00
Alex Bradbury 6121ddcb93 [RISCV] Re-organise calling convention tests
Re-organise calling convention tests to prepare for ilp32f and ilp32d hard
float ABI tests. It's also clear that we need to introduce similar tests for
lp64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354323 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-19 13:47:19 +00:00
George Rimar 67f1133492 Fix BB after r354319 "[yaml2obj] - Do not skip zeroes blocks if there are relocations against them."
Fix: move the test to x86 folder. 
Seems it is needed, because llvm-objdump invocation used in test has -D (disasm) flag.

BB: http://lab.llvm.org:8011/builders/clang-hexagon-elf/builds/23016

/local/buildbot/slaves/hexagon-build-02/clang-hexagon-elf/stage1/bin/llvm-objdump: 
error: '/local/buildbot/slaves/hexagon-build-02/clang-hexagon-elf/stage1/test/tools/llvm-objdump/Output/disasm-zeroes-relocations.test.tmp': 
can't find target: : error: unable to get target for 'x86_64--', see --version and --triple.
.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354322 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-19 13:27:06 +00:00
George Rimar 1cb4de41ab [yaml2obj] - Do not skip zeroes blocks if there are relocations against them.
This is for -D -reloc combination.

With this patch, we do not skip the zero bytes that have a relocation against
them when -reloc is used. If -reloc is not used, then the behavior will be the same.

Differential revision: https://reviews.llvm.org/D58174

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354319 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-19 12:38:36 +00:00
George Rimar ec70b5d16b [yaml2obj] - Do not ignore explicit addresses for .dynsym and .dynstr
This fixes https://bugs.llvm.org/show_bug.cgi?id=40339

Previously if the addresses were set in YAML they were ignored for
.dynsym and .dynstr sections. The patch fixes that.

Differential revision: https://reviews.llvm.org/D58168

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354318 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-19 12:15:04 +00:00
Diana Picus f2e80bf41c [ARM GlobalISel] Support G_PHI for Thumb2
Same as arm mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354310 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-19 10:26:47 +00:00
Jessica Paquette 1d3cbd7331 [GlobalISel][AArch64] Legalize + select some llvm.ctlz.* intrinsics
Legalize/select llvm.ctlz.*

Add select-ctlz to show that we actually select them. Update arm64-clrsb.ll and
arm64-vclz.ll to show that we perform valid transformations in optimized builds,
and document where GISel can improve.

Differential Revision: https://reviews.llvm.org/D58155

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354299 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 23:33:24 +00:00
Sanjay Patel 09f3b5ecb1 [CGP] form usub with overflow from sub+icmp
The motivating x86 cases for forming the intrinsic are shown in PR31754 and PR40487:
https://bugs.llvm.org/show_bug.cgi?id=31754
https://bugs.llvm.org/show_bug.cgi?id=40487
..and those are shown in the IR test file and x86 codegen file.

Matching the usubo pattern is harder than uaddo because we have 2 independent values rather than a def-use.

This adds a TLI hook that should preserve the existing behavior for uaddo formation, but disables usubo
formation by default. Only x86 overrides that setting for now although other targets will likely benefit
by forming usbuo too.

Differential Revision: https://reviews.llvm.org/D57789

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354298 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 23:33:05 +00:00
Changpeng Fang 1e3c4790ab AMDGPU: Use MachineInstr::mayAlias to replace areMemAccessesTriviallyDisjoint in LoadStoreOptimizer pass.
Summary:
  This is to fix a memory dependence bug in LoadStoreOptimizer.

Reviewers:
  arsenm, rampitec

Differential Revision:
  https://reviews.llvm.org/D58295

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354295 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 23:00:26 +00:00
Matt Arsenault b1b624d08a GlobalISel: Implement widenScalar for g_extract scalar results
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354293 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 22:39:27 +00:00
Sanjay Patel 74ea62225d [x86] split more v8f32/v8i32 shuffles in lowering
Similar to D57867 - this is a small patch with lots of test diffs.
With half-vector-width narrowing potential, using an extract + 128-bit vshufps
is a win because it replaces a 256-bit shuffle with a 128-bit shufle.

This seems like it should be a win even for targets with 'fast-variable-shuffle',
but we are intentionally deferring that to an independent change to make sure
that is true.

Differential Revision: https://reviews.llvm.org/D58181

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354279 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 16:46:12 +00:00
Sanjay Patel 5f8e90cc7e Revert "[InstCombine] reduce even more unsigned saturated add with 'not' op"
This reverts commit 079b610c29b4a428b3ae7b64dbac0378facf6632.
Bots are failing after this change on a stage 2 compile of clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354277 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 16:04:22 +00:00
Sanjay Patel 7e06b426b6 [InstCombine] reduce even more unsigned saturated add with 'not' op
We want to use the sum in the icmp to allow matching with
m_UAddWithOverflow and eliminate the 'not'. This is discussed
in D51929 and is another step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613

  Name: uaddsat, -1 fval
  %notx = xor i32 %x, -1
  %a = add i32 %x, %y
  %c = icmp ugt i32 %notx, %y
  %r = select i1 %c, i32 %a, i32 -1
  =>
  %a = add i32 %x, %y
  %c2 = icmp ugt i32 %y, %a
  %r = select i1 %c2, i32 -1, i32 %a

  Name: uaddsat, -1 fval + ult
  %notx = xor i32 %x, -1
  %a = add i32 %x, %y
  %c = icmp ult i32 %y, %notx
  %r = select i1 %c, i32 %a, i32 -1
  =>
  %a = add i32 %x, %y
  %c2 = icmp ugt i32 %y, %a
  %r = select i1 %c2, i32 -1, i32 %a

https://rise4fun.com/Alive/nTp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354276 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 15:21:39 +00:00
Andrea Di Biagio 628018073d [MCA] Correctly update register definitions in the PRF after move elimination.
This patch fixes a bug where register writes performed by optimizable register
moves were sometimes wrongly treated like partial register updates.  Before this
patch, llvm-mca wrongly predicted a 1.50 IPC for test reg-move-elimination-6.s
(added by this patch).  With this patch, llvm-mca correctly updates the register
defintions in the PRF, and the IPC for that test is now correctly reported as 2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354271 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 14:15:25 +00:00
Clement Courbet 3cfd39d61c Revert r354244 "[DAGCombiner] Eliminate dead stores to stack."
Breaks some bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354245 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 08:24:29 +00:00
Clement Courbet 89d8d90473 [DAGCombiner] Eliminate dead stores to stack.
Summary:
A store to an object whose lifetime is about to end can be removed.

See PR40550 for motivation.

Reviewers: niravd

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D57541

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354244 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-18 07:59:01 +00:00
Sanjay Patel 043364a681 [InstCombine] add even more tests for unsigned saturated add; NFC
The pattern-matching from rL354221 / rL354224 doesn't cover
these, so we're up to 8 different commuted possibilities.

There may still be 1 more variant of this pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354236 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-17 20:01:59 +00:00
Craig Topper 8201c54c00 [X86] In FP_TO_INTHelper, when moving data from SSE register to X87 register file via the stack, use the same stack slot we use for the integer conversion.
No need for a separate stack slot. The lifetimes don't overlap.

Also fix the MachinePointerInfo for the final load after the integer conversion to indicate it came from the stack slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354234 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-17 19:23:49 +00:00
Max Kazantsev f6e5376a87 [TEST] Remove 2>&1 from tests
Avoid confusing CHECKS with debug dumps of sets that can be printed differently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354229 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-17 18:22:00 +00:00
Sanjay Patel 6de5879eec [InstCombine] reduce more unsigned saturated add with 'not' op
We want to use the sum in the icmp to allow matching with
m_UAddWithOverflow and eliminate the 'not'. This is discussed
in D51929 and is another step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613

  Name: not op
  %notx = xor i32 %x, -1
  %a = add i32 %x, %y
  %c = icmp ult i32 %notx, %y
  %r = select i1 %c, i32 -1, i32 %a
  =>
  %a = add i32 %x, %y
  %c2 = icmp ult i32 %a, %y
  %r = select i1 %c2, i32 -1, i32 %a

  Name: not op ugt
  %notx = xor i32 %x, -1
  %a = add i32 %x, %y
  %c = icmp ugt i32 %y, %notx
  %r = select i1 %c, i32 -1, i32 %a
  =>
  %a = add i32 %x, %y
  %c2 = icmp ult i32 %a, %y
  %r = select i1 %c2, i32 -1, i32 %a

https://rise4fun.com/Alive/niom

(The matching here is still incomplete.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354224 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-17 16:48:50 +00:00
Sanjay Patel 5c63b2cd25 [InstCombine] add more tests for unsigned saturated add; NFC
Extend the pattern-matching from rL354219 / rL354221.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354223 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-17 16:44:11 +00:00
Sanjay Patel 47d3493536 [InstCombine] reduce unsigned saturated add with 'not' op
We want to use the sum in the icmp to allow matching with
m_UAddWithOverflow and eliminate the 'not'. This is discussed
in D51929 and is another step towards solving PR14613:
https://bugs.llvm.org/show_bug.cgi?id=14613

(The matching here is incomplete. Trying to take minimal steps
to make sure we don't induce infinite looping from existing
canonicalizations of the 'select'.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354221 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-17 15:58:48 +00:00
Sanjay Patel 58ac5f316a [InstCombine] add tests for unsigned saturated add; NFC
We're missing IR canonicalizations for this op as shown in D51929.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354219 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-17 15:09:41 +00:00
Craig Topper 42724d04c4 [X86] When type legalizing the result of a i64 fp_to_uint on 32-bit targets. Generate all of the ops as i64 and let them be legalized.
No need to manually split everything. We can let the type legalizer work for us.

The test change seems to be caused by some DAG ordering issue that was previously circumventing a one use check in LowerSELECT where FP selects are turned into blends if the setcc has one use. But it was running after an integer select and the same setcc had been legalized to cmov and X86SISD::CMP. This dropped the use count of the setcc, but wasn't what was intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354197 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-16 08:25:42 +00:00
Dave Lee d26e1d9d95 llvm-nm: Observe -no-llvm-bc for archive members
Summary:
This change fixes the `-no-llvm-bc` flag to work with object files within
archives. Currently the `-no-llvm-bc` flag works for regular object files, but
not static libraries, where it continues to show bitcode symbol info.

Original support was added in D4371.

Reviewers: compnerd, smeenai, pcc

Reviewed By: compnerd

Subscribers: rupprecht, keith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D48798

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354196 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-16 06:59:49 +00:00
Craig Topper df61a5888f [X86] Don't prevent load folding for cvtsi2ss/cvtsi2sd based on hasPartialRegUpdate.
Preventing the load fold won't fix the partial register update since the
input we can fold is a GPR. So it will do nothing to prevent a false dependency
on an XMM register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354193 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-16 03:34:54 +00:00
Craig Topper a9c85cb3b8 [X86] Don't set exception mask bits when modifying FPCW to change rounding mode for fp->int conversion
When we need to do an fp->int conversion using x87 instructions, we need to temporarily change the rounding mode to 0b11 and perform a store. To do this we save the old value of the fpcw to the stack, then set the fpcw to 0xc7f, do the store, then restore fpcw. But the 0xc7f value forces the exception mask bits 1. While this is what they would be in the default FP environment, as we move to support changing the FP environments, we shouldn't make this assumption.

This patch changes the code to explicitly OR 0xc00 with the old value so that only the rounding mode is changed. Unfortunately, this requires two stack temporaries instead of one. One to hold the old value and one to hold the new value. Without two stack temporaries we would need an additional GPR. We already need one to do the OR operation in. This is similar to what gcc and icc do for this operation. Though they are both better at reusing the stack temporaries when there are multiple truncates in a function(or at least in a basic block)

Differential Revision: https://reviews.llvm.org/D57788

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354178 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 21:59:33 +00:00
Philip Reames 5c802fd2ca [InstCombine] Convert atomicrmws to xchg or store where legal
Implement two more transforms of atomicrmw:
1) We can convert an atomicrmw which produces a known value in memory into an xchg instead.
2) We can convert an atomicrmw xchg w/o users into a store for some orderings.

Differential Revision: https://reviews.llvm.org/D58290



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354170 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 21:23:51 +00:00
Nirav Dave 45ef910a26 [X86] Fix LowerAsmOutputForConstraint.
Summary:
Update Flag when generating cc output.

Fixes PR40737.

Reviewers: rnk, nickdesaulniers, craig.topper, spatel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58283

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354163 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 20:01:55 +00:00
Jonas Paulsson 9129f92efa Recommit "[SystemZ] Do not emit VEXTEND or VROUND nodes without vector support."
It seems there were some problem with using a .mir test. For some reason
doing '-stop-before=codegenprepare' and then '-start-before=codegenprepare'
on the output .mir file results in the NoVRegs Property after instruction
selection.

Recommitting the same test as an .ll file instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354160 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 19:13:55 +00:00
Vedant Kumar c26f76b367 [CodeExtractor] Do not lift lifetime.end markers for region inputs
If a lifetime.end marker occurs along one path through the extraction
region, but not another, then it's still incorrect to lift the marker,
because there is some path through the extracted function which would
ordinarily not reach the marker. If the call to the extracted function
is in a loop, unrolling can cause inputs to the function to become
optimized out as undef after the first iteration.

To prevent incorrect stack slot merging in the calling function, it
should be sufficient to lift lifetime.start markers for region inputs.
I've tested this theory out by doing a stage2 check-all with randomized
splitting enabled.

This is a follow-up to r353973, and there's additional context for this
change in https://reviews.llvm.org/D57834.

rdar://47896986

Differential Revision: https://reviews.llvm.org/D58253

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354159 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 18:46:58 +00:00
Vedant Kumar 45c9fb9375 [HotColdSplit] Schedule splitting late to fix perf regression
With or without PGO data applied, splitting early in the pipeline
(either before the inliner or shortly after it) regresses performance
across SPEC variants. The cause appears to be that splitting hides
context for subsequent optimizations.

Schedule splitting late again, in effect reversing r352080, which
scheduled the splitting pass early for code size benefits (documented in
https://reviews.llvm.org/D57082).

Differential Revision: https://reviews.llvm.org/D58258

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354158 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 18:46:44 +00:00
Philip Reames f9f8ba4f3b [Tests] Demonstrate more missing atomicrmw transforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354146 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 17:11:30 +00:00
Sanjay Patel d8794196af [InstCombine] fix crash while trying to narrow a binop of shuffles (PR40734)
https://bugs.llvm.org/show_bug.cgi?id=40734

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354144 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 16:31:55 +00:00
Matt Arsenault c86376b897 GlobalISel: Fix inadequate verification of g_build_vector
Testing based on the total size of the elements failed to catch a few
invalid scenarios, so explicitly check the number of elements/operands
and types.

This failed to catch situations like
<4 x s16> = G_BUILD_VECTOR s32, s32 since the total size added
up. This also would fail to catch an implicit conversion between
pointers and scalars.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354139 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 15:24:34 +00:00
Matt Arsenault 57078b6e3a Try to organize MachineVerifier tests
The Verifier is separate from the MachineVerifier, so move it to a
different directory. Some other verifier tests were scattered in
target codegen tests as well (although I'm sure I missed some). Work
towards using a more consistent naming scheme to make it clearer where
the gaps still are for generic instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354138 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 15:24:31 +00:00
Sam Parker 1b41b25fc1 [BPI] Look through bitcasts in calcZeroHeuristic
Constant hoisting may have hidden a constant behind a bitcast so that
it isn't folded into its users. However, this prevents BPI from
calculating some of its heuristics that are based upon constant
values. So, I've added a simple helper function to look through these
casts.

Differential Revision: https://reviews.llvm.org/D58166


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354119 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 11:50:21 +00:00
Simon Pilgrim 7e13a67ffc [X86][AVX] lowerShuffleAsLanePermuteAndPermute - fully populate the lane shuffle mask (PR40730)
As detailed on PR40730, we are not correctly filling in the lane shuffle mask (D53148/rL344446) - we fill in for the correct src lane but don't add it to the correct mask element, so any reference to the correct element is likely to see an UNDEF mask index.

This allows constant folding to propagate UNDEFs prior to the lane mask being (correctly) lowered to vperm2f128.

This patch fixes the issue by fully populating the lane shuffle mask - this is more than is necessary (if we only filled in the required mask elements we might be able to match other shuffle instructions - broadcasts etc.), but its the most cautious approach as this needs to be cherrypicked into the 8.0.0 release branch.

Differential Revision: https://reviews.llvm.org/D58237

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354117 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 11:39:21 +00:00
Diana Picus 3cbeb27e3b [ARM GlobalISel] Support branches for Thumb2
Just like arm mode, but with different opcodes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354113 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 10:24:03 +00:00
Alex Bradbury 384f64397f [RISCV] Add assembler support for LA pseudo-instruction
This patch also introduces the emitAuipcInstPair helper, which is then used
for both emitLoadAddress and emitLoadLocalAddress.

Differential Revision: https://reviews.llvm.org/D55325
Patch by James Clarke.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354111 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 09:53:32 +00:00
Alex Bradbury 6ea38efaaa [RISCV] Support assembling %got_pcrel_hi operator
Differential Revision: https://reviews.llvm.org/D55279
Patch by James Clarke.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354110 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 09:43:46 +00:00
Sam Parker 52cd80dbc1 [ARM CGP] Fix ConvertTruncs
ConvertTruncs is used to replace a trunc for an AND mask, however
this function wasn't working as expected. By performing the change
later, we can create a wide type integer mask instead of a narrow -1
value, which could then be simply removed (incorrectly). Because we
now perform this action later, it's necessary to cache the trunc type
before we perform the promotion.

Differential Revision: https://reviews.llvm.org/D57686


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354108 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 09:04:39 +00:00
Max Kazantsev 5b6bbc8515 [TEST] Update test comments, refactor checks with update_test_checks.py
This patch changes messages in guards-related tests to adequately reflect
reality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354101 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 07:06:52 +00:00
Francis Visoiu Mistrih 5716349e30 Revert "[SystemZ] Do not emit VEXTEND or VROUND nodes without vector support."
This reverts commit aa0b77d3395dc6ab91647138139c1a15a3aa088d.

This fails to pass the machine verifier:
http://green.lab.llvm.org/green/job/clang-stage1-cmake-RA-expensive/13579/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354096 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-15 03:01:09 +00:00
Konstantin Zhuravlyov 1d02248c5f AMDGPU: Set ABI version to 1 for code object v3
Differential Revision: https://reviews.llvm.org/D57811


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354085 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-14 23:56:04 +00:00
Matt Davis 925de09633 [symbolizer] Avoid collecting symbols belonging to invalid sections.
Summary:
llvm-symbolizer would originally report symbols that belonged to an invalid object file section.
Specifically the case where: `*Symbol.getSection() == ObjFile.section_end()`
This patch prevents the Symbolizer from collecting symbols that belong to invalid sections.

The test  (from PR40591) introduces a case where two symbols have address 0,
one symbol is defined, 'foo', and the other is not defined, 'bar'.  This patch will cause
the Symbolizer to keep 'foo' and ignore 'bar'.

As a side note, the logic for adding symbols to the Symbolizer's store
(`SymbolizableObjectFile::addSymbol`) replaces symbols with the
same <address, size> pair.  At some point that logic should be revisited as in the
aforementioned case, 'bar' was overwriting 'foo' in the Symbolizer's store,
and 'foo' was forgotten.

This fixes PR40591

Reviewers: jhenderson, rupprecht

Reviewed By: rupprecht

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58146

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354083 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-14 23:50:35 +00:00
Sanjay Patel aea63d5e2d [x86] add tests for extractelement of FP; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354077 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-14 23:17:22 +00:00
Matt Arsenault 81e2f59c84 Replace gcroot verifier tests
These haven't been checking anything useful and have been testing the
wrong failure reason for many years. Replace them with something which
stresses what is actually implemented in the verifier now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354070 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-14 22:41:01 +00:00
Matt Arsenault 217f03f322 AMDGPU/GlobalISel: Fix RegBankSelect for GEP.
This is basically a pointer typed add, so shouldn't be any different.
This was assuming everything was an SGPR, which is not true.

Also cleanup legality for GEP. I don't seem to be seeing the problem
the hack marking s64 as a legal pointer type the comment mentions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354067 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-14 22:24:28 +00:00
Stanislav Mekhanoshin 2f5fd7e3bd [AMDGPU] Ressociate 'add (add x, y), z' to use SALU
Reassociate adds to collect scalar operands in a single
instruction when possible. That will result in a scalar
add followed by vector instead of two vector adds, thus
better utilizing SALU.

Differential Revision: https://reviews.llvm.org/D58220

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354066 91177308-0d34-0410-b5e6-96231b3b80d8
2019-02-14 22:11:25 +00:00