Commit Graph

156950 Commits

Author SHA1 Message Date
Craig Topper
d024fd1406 [X86] Attempt to fix signed and unsigned comparison warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318010 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13 02:19:13 +00:00
Craig Topper
5f9380c926 [X86] Use sse_load_f32/f64 in patterns for the memory forms of VRNDSCALESS/SD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318009 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13 02:03:01 +00:00
Craig Topper
e6cdd20402 [X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round intrinsics.
The VRNDSCALE instructions implement a superset of the (V)ROUND instructions. They are equivalent if the upper 4-bits of the immediate are 0.

This patch lowers the legacy intrinsics to the VRNDSCALE ISD node and masks the upper bits of the immediate to 0. This allows us to take advantage of the larger register encoding space.

We should maybe consider converting VRNDSCALE back to VROUND in the EVEX to VEX pass if the extended registers are not being used.

I notice some load folding opportunities being missed for the VRNDSCALESS/SD instructions that I'll try to fix in future patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318008 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13 02:03:00 +00:00
Craig Topper
fa371074cb [X86] Split VRNDSCALE/VREDUCE/VGETMANT/VRANGE ISD nodes into versions with and without the rounding operand. NFCI
I want to reuse the VRNDSCALE node for the legacy SSE rounding intrinsics so that those intrinsics can use EVEX instructions. All of these nodes share tablegen multiclasses so I split them all so that they all remain similar in their implementations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318007 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13 02:02:58 +00:00
Matt Arsenault
1cedae7c8d Fix some misc. -enable-var-scope violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318006 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13 01:47:52 +00:00
Matt Arsenault
d8f8d0c326 AMDGPU: Select d16 loads into low component of register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318005 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-13 00:22:09 +00:00
Matt Arsenault
19f503cb02 AMDGPU: Fix -enable-var-scope violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318004 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12 23:53:44 +00:00
Matt Arsenault
d9fc007ba5 AMDGPU: Fix missing gfx9 atomic inc/dec tests
The global instructions weren't tested. Plus there
were also some -enable-var-scope violations and
broken check prefixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318003 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12 23:40:12 +00:00
Craig Topper
5d947c3894 [X86] Add an X86ISD::RANGES opcode to use for the scalar intrinsics.
This fixes a bug where we selected packed instructions for scalar intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317999 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12 18:51:09 +00:00
Craig Topper
fc0c3a0fe7 [X86] Add test cases and command lines demonstrating how we accidentally select vrangeps/vrangepd from vrangess/vrangesd instrinsics when the rounding mode is CUR_DIRECTION
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317998 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12 18:51:08 +00:00
Craig Topper
d1d7d9c52d [X86] Remove some no longer needed intrinsic lowering code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317997 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12 18:51:06 +00:00
Mandeep Singh Grang
9c71f59113 [llvm] Remove redundant return [NFC]
Reviewers: davidxl, olista01, Eugene.Zelenko

Reviewed By: Eugene.Zelenko

Subscribers: sdardis, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D39917

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317995 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12 03:47:50 +00:00
Craig Topper
5b555fa10e [InstCombine] Teach visitICmpInst to not break integer absolute value idioms
Summary:
This patch adds an early out to visitICmpInst if we are looking at a compare as part of an integer absolute value idiom. Similar is already done for min/max.

In the particular case I observed in a benchmark we had an absolute value of a load from an indexed global. We simplified the compare using foldCmpLoadFromIndexedGlobal into a magic bit vector, a shift, and an and. But the load result was still used for the select and the negate part of the absolute valute idiom. So we overcomplicated the code and lost the ability to recognize it as an absolute value.

I've chosen a simpler case for the test here.

Reviewers: spatel, davide, majnemer

Reviewed By: spatel

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D39766

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317994 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-12 02:28:21 +00:00
Craig Topper
6e10efc50e [X86] Use vrndscaleps/pd for 128/256 ffloor/ftrunc/fceil/fnearbyint/frint when avx512vl is enabled.
This matches what we do for scalar and 512-bit types.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317991 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 21:44:51 +00:00
Craig Topper
04bd4860e0 [X86] Remove avx512-round.ll. The 512-bit rounding tests are now in vec_floor.ll with 128/256 sizes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317990 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 21:44:50 +00:00
Craig Topper
1b52c8d11b [X86] Add avx512vl command line to vec_floor.ll. Add 512-bit test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317989 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 21:44:49 +00:00
Craig Topper
54c9ba4c53 [X86] Add avx512f command line to rounding-ops.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317988 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 21:44:48 +00:00
Craig Topper
758e6564c6 [X86] Regenerate rounding-ops.ll with update_llc_test_checks.py
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317987 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 21:44:47 +00:00
Simon Pilgrim
90159860ad [X86] Attempt to match multiple binary reduction ops at once. NFCI
matchBinOpReduction currently matches against a single opcode, but we already have a case where we repeat calls to try to match against AND/OR and I'll be shortly adding another case for SMAX/SMIN/UMAX/UMIN (D39729).

This NFCI patch alters matchBinOpReduction to try and pattern match against any of the provided list of candidate bin ops at once to save time.

Differential Revision: https://reviews.llvm.org/D39726

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317985 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 18:16:55 +00:00
Craig Topper
dbf8de9323 [X86] Add scalar register class versions of VRNDSCALE instructions and rename the existing versions to _Int.
This is consistent with out normal implementation of scalar instructions.

While there disable load folding for the patterns with IMPLICIT_DEF unless optimizing for size which is also our standard practice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317977 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 08:24:15 +00:00
Craig Topper
d009633224 [X86] Regenerate avx512-round.ll test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317976 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 08:24:13 +00:00
Craig Topper
4181ca8d33 [X86] Inline some SDNode operand multiclass operands that don't vary. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317975 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 08:24:12 +00:00
Craig Topper
e9276ec971 [X86] Set the execution domain for VFPCLASS to SSEPackedSingle/Double.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317974 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 06:57:44 +00:00
Craig Topper
10b0bc2481 [X86] Set the execution domain for vptest instruction to the integer domain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317973 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 06:19:12 +00:00
Daniel Sanders
8f5a591f29 [globalisel][tablegen] Import signextload and zeroextload.
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to
correct situations where SelectionDAG and GlobalISel disagree on
representation. For example, it would rewrite:
  (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16>
to:
  (sext:i32 (load:i16 $ptr)<<unindexedload>>)

I'd have preferred to replace the fragments and have the expansion happen
naturally as part of PatFrag expansion but the type inferencing system can't
cope with loads of types narrower than those mentioned in register classes.
This is because the SDTCisInt's on the sext constrain both the result and
operand to the 'legal' integer types (where legal is defined as 'a register
class can contain the type') which immediately rules the narrower types out.
Several targets (those with only one legal integer type) would then go on to
crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types
for the result of the extend.

Also, improve isObviouslySafeToFold() slightly to automatically return true for
neighbouring instructions. There can't be any re-ordering problems if
re-ordering isn't happenning. We'll need to improve it further to handle
sign/zero-extending loads when the extend and load aren't immediate neighbours
though.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317971 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 03:23:44 +00:00
Craig Topper
975df6ffda [X86] Correct the execution domain on ROUND/VROUND instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317968 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 02:26:05 +00:00
Craig Topper
20487ae90c [X86] Remove the default for one of the arguments to some tablegen multiclasses. NFC
No one ever uses this default and probably shouldn't since it sets the execution domain to generic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317967 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 02:26:02 +00:00
NAKAMURA Takumi
b99884c4a5 llvm/Support/TargetParser.h: Fix -fmodules build in rL317900.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317966 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 02:05:47 +00:00
Tony Tye
995388dd36 [AMDGPU] Correct targets that support XNACK
Differential Revision: https://reviews.llvm.org/D39887


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317955 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-11 00:50:32 +00:00
Craig Topper
aa795776c9 [SelectionDAG] Make getUniformBase in SelectionDAGBuilder fail if any of the middle GEP indices are non-constant.
This is a fix for a bug in r317947. We were supposed to check that all the indices are are constant 0, but instead we're only make sure that indices that are constant are 0. Non-constant indices are being ignored.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317950 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 23:36:56 +00:00
Zachary Turner
d3e2d8422a Update test_debuginfo.pl script to point to new tree location.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317949 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 23:13:14 +00:00
Craig Topper
9d3d840987 [SelectionDAG] Teach SelectionDAGBuilder's getUniformBase for gather/scatter handling to accept GEPs with more than 2 operands if the middle operands are all 0s
Currently we can only get a uniform base from a simple GEP with 2 operands. This causes us to miss address folding opportunities for simple global array accesses as the test case shows.

This patch adds support for larger GEPs if the other indices are 0 since those don't require any additional computations to be inserted.

We may also want to handle constant splats of zero here, but I'm leaving that for future work when I have a real world example.

Differential Revision: https://reviews.llvm.org/D39911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317947 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 22:50:50 +00:00
Evgeniy Stepanov
e3ff9fbdba [asan] Use dynamic shadow on 32-bit Android.
Summary:
The following kernel change has moved ET_DYN base to 0x4000000 on arm32:
https://marc.info/?l=linux-kernel&m=149825162606848&w=2

Switch to dynamic shadow base to avoid such conflicts in the future.

Reserve shadow memory in an ifunc resolver, but don't use it in the instrumentation
until PR35221 is fixed. This will eventually let use save one load per function.

Reviewers: kcc

Subscribers: aemerson, srhines, kubamracek, kristof.beyls, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D39393

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317943 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 22:27:48 +00:00
Martin Storsjo
4a22e748f2 [llvm-cvtres] Add support for ARM64
Also change some default cases into llvm_unreachable in
WindowsResourceCOFFWriter, to make it easier to find if they
are triggerd from within e.g. lld, which supported ARM64 earlier
than llvm-cvtres did.

Differential Revision: https://reviews.llvm.org/D39892

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317942 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 22:27:41 +00:00
Mitch Phillips
7c7bb61bbf [cfi-verify] Made FileAnalysis operate on a GraphResult rather than build one and validate it.
Refactors the behaviour of building graphs out of FileAnalysis, allowing for analysis of the GraphResult by the callee without having to rebuild the graph. Means when we want to analyse the constructed graph (planned for later revisions), we don't do repeated work.

Also makes CFI verification in FileAnalysis now return an enum that allows us to differentiate why something failed, not just that it did/didn't fail.

Reviewers: vlad.tsyrklevich

Subscribers: kcc, pcc, llvm-commits

Differential Revision: https://reviews.llvm.org/D39764

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317927 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 21:00:22 +00:00
Amaury Sechet
24331f974f [DAGcombine] Do not replace truncate node by itself when doing constant folding, this trigger needless extra rounds of combine for nothing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317926 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:59:53 +00:00
Zachary Turner
cbf08c741a [debuginfo-tests] Make debuginfo-tests work in a standard configuration.
Previously, debuginfo-tests was expected to be checked out into
clang/test and then the tests would automatically run as part of
check-clang.  This is not a standard workflow for handling
external projects, and it brings with it some serious drawbacks
such as the inability to depend on things other than clang, which
we will need going forward.

The goal of this patch is to migrate towards a more standard
workflow.  To ease the transition for build bot maintainers,
this patch tries not to break the existing workflow, but instead
simply deprecate it to give maintainers a chance to update
the build infrastructure.

Differential Revision: https://reviews.llvm.org/D39605

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317925 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:57:57 +00:00
Tony Tye
2f2cb6b2a2 [AMDGPU] AMDGPUUsage.rst minor corrections
Differential Revision: https://reviews.llvm.org/D39887


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317924 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:51:43 +00:00
Davide Italiano
4013502618 [SimplifyCFG] Use auto * when the type is obvious. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317923 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:46:21 +00:00
Krzysztof Parzyszek
0f47b426bf Recommit r317904: [Hexagon] Create HexagonISelDAGToDAG.h, NFC
The Windows builder did not reconstruct the HexagonGenDAGISel.inc file
after the TableGen binary has changed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317921 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:09:46 +00:00
Konstantin Zhuravlyov
8f4df2fc0b AMDGPU/NFC: Split Processors.td into GCNProcessors.td and R600Processors.td
Differential Revision: https://reviews.llvm.org/D39880


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317920 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 20:01:58 +00:00
Daniel Neilson
6850d9138b Expand IRBuilder interface for atomic memcpy to require pointer alignments. (NFC)
Summary:
 The specification of the @llvm.memcpy.element.unordered.atomic intrinsic requires
that the pointer arguments have alignments of at least the element size. The existing
IRBuilder interface to create a call to this intrinsic does not allow for providing
the alignment of these pointer args. Having an interface that makes it easy to
construct invalid intrinsic calls doesn't seem sensible, so this patch simply
adds the requirement that one provide the argument alignments when using IRBuilder
to create atomic memcpy calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317918 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:38:12 +00:00
Krzysztof Parzyszek
e8afbbe959 Revert "[Hexagon] Create HexagonISelDAGToDAG.h, NFC"
This reverts r317904: broke Windows build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317916 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:27:18 +00:00
Craig Topper
33a8b75763 [X86] Merge the template method selectAddrOfGatherScatterNode into selectVectorAddr. NFCI
Just need to initialize a couple variables differently based on the node type. No need for a whole separate template method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317915 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:26:04 +00:00
Adrian Prantl
23bd33afd4 Add back target triple to test which I accidentally removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317912 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:22:02 +00:00
Sanjoy Das
7af26ab717 [CVP] Remove some {s|u}add.with.overflow checks.
Summary:
This adds logic to CVP to remove some overflow checks.  It uses LVI to remove
operations with at least one constant.  Specifically, this can remove many
overflow intrinsics immediately following an overflow check in the source code,
such as:

if (x < INT_MAX)
    ... x + 1 ...

Patch by Joel Galenson!

Reviewers: sanjoy, regehr

Reviewed By: sanjoy

Subscribers: fhahn, pirama, srhines, llvm-commits

Differential Revision: https://reviews.llvm.org/D39483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317911 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:13:35 +00:00
Mandeep Singh Grang
12ca5fd711 [RISCV] Silence an unused variable warning in release builds [NFC]
Summary:
Also minor cleanups:
1. Avoided multiple calls to Fixup.getKind()
2. Avoided multiple calls to getFixupKindInfo()
3. Removed a redundant return.

Reviewers: asb, apazos

Reviewed By: asb

Subscribers: rbar, johnrusso, llvm-commits

Differential Revision: https://reviews.llvm.org/D39881

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317908 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 19:09:28 +00:00
Craig Topper
1924c0ebef [X86] Add test case to demonstrate failure to fold the address computation of a simple gather from a global array. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317905 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 18:48:18 +00:00
Krzysztof Parzyszek
38f2fbe008 [Hexagon] Create HexagonISelDAGToDAG.h, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317904 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 18:39:45 +00:00
Krzysztof Parzyszek
9911901fcd Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc
This patch adds the ability to include the member function declarations
in the instruction selector class separately from the member bodies.

Defining GET_DAGISEL_DECL macro to any value will only include the member
declarations. To include bodies, define GET_DAGISEL_BODY macro to be the
selector class name. Example:

  class FooDAGToDAGISel : public SelectionDAGISel {
    // Pull in declarations only.
    #define GET_DAGISEL_DECL
    #include "FooISelDAGToDAG.inc"
  };

  // Include the function bodies (with names qualified with the provided
  // class name).
  #define GET_DAGISEL_BODY FooDAGToDAGISel
  #include "FooISelDAGToDAG.inc"

When neither of the two macros are defined, the function bodies are emitted
inline (in the same way as before this patch).

Differential Revision: https://reviews.llvm.org/D39596


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317903 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-10 18:36:04 +00:00