Commit Graph

161223 Commits

Author SHA1 Message Date
Jonas Paulsson dbd628b4c7 [SystemZ] Improved debug dumping during post-RA scheduling.
Review: Ulrich Weigand

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326878 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-07 08:39:00 +00:00
Clement Courbet 0ad2b2f8bf [X86] Add IMUL scheduling info on sandybridge, fix it on >=haswell.
Summary:
Only IMUL16rri uses an extra P0156. IMUL32* and IMUL16rr only use
P1.
This was computed using https://github.com/google/EXEgesis/blob/master/exegesis/tools/compute_itineraries.cc

This can easily be validated by running perf on the following code:

```
int main(int argc, char**argv) {
  int a = argc;
  int b = argc;
  int c = argc;
  int d = argc;

  for (int i = 0; i < LOOP_ITERATIONS; ++i) {
    asm volatile(
      R"(
        .rept 10000
        imull $0x2, %%edx, %%eax
        imull $0x2, %%ecx, %%ebx
        imull $0x2, %%eax, %%edx
        imull $0x2, %%ebx, %%ecx
        .endr
      )"
      : "+a"(a), "+b"(b), "+c"(c), "+d"(d)
      :
      :);
  }
  return a+b+c+d;
}
```
-> test.cc

perf stat -x, -e cycles --pfm-events=uops_executed_port:port_0:u,uops_executed_port:port_1:u,uops_executed_port:port_2:u,uops_executed_port:port_3:u,uops_executed_port:port_4:u,uops_executed_port:port_5:u,uops_executed_port:port_6:u,uops_executed_port:port_7:u test

Reviewers: craig.topper, RKSimon, gadi.haber

Subscribers: llvm-commits, gchatelet, chandlerc

Differential Revision: https://reviews.llvm.org/D43460

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326877 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-07 08:14:02 +00:00
Aaron Smith 71e93dfc4b [llvm-pdbdump] Add guard for null pointers and remove unused code
Summary: This avoids crashing when a user tries to dump a pdb with the `-native` option.

Reviewers: zturner, llvm-commits, rnk

Reviewed By: zturner

Subscribers: mgrang

Differential Revision: https://reviews.llvm.org/D44117

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326863 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-07 02:23:08 +00:00
Evgeny Stupachenko b86930c909 Add early exit on reassociation of 0 expression.
Summary:

Before the patch a try to reassociate ((v * 16) * 0) * 1 fall into infinite loop

Reviewers: pankajchawla

Differential Revision: http://reviews.llvm.org/D41467

From: Evgeny Stupachenko <evstupac@gmail.com>
                         <evgeny.v.stupachenko@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326861 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-07 02:17:08 +00:00
Aaron Smith 611e8053e2 [DebugInfoPDB] Add DIA implementation for getSrcLineOnTypeDefn
Summary: This helps to determine the line number for a PDB type with definition

Reviewers: zturner, llvm-commits, rnk

Reviewed By: zturner

Subscribers: rengolin, JDevlieghere

Differential Revision: https://reviews.llvm.org/D44119

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326857 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-07 00:33:09 +00:00
Eugene Zelenko 7c9054610e [Transforms] Add missing header for InstructionCombining.cpp, in order to export LLVMInitializeInstCombine as extern "C". Fixes PR35947.
Patch by Brenton Bostick.

Differential revision: https://reviews.llvm.org/D44140


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326843 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 23:06:13 +00:00
Craig Topper e2eaa5bc5c [X86] Fix a typo in Host.cpp that causes us to misidentify KNL, Silvermont, Goldmont and probably other CPUs for -march=native
I think most of the Intel Core CPUs and recent AMD CPUs are unaffected. All the CPUs that have a "subtype" should work. The ones that were broken are the ones that are a "type" with no subtypes.

Fixes PR36619.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326840 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 22:45:31 +00:00
Paul Robinson c7343198ca Reapply "[DWARFv5] Emit file 0 to the line table."
Fixes the bug found by asan. Also XFAIL the new test for Darwin,
which is stuck on DWARF v2, and fix up other tests so they stop
failing on Windows.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326839 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 22:37:45 +00:00
Simon Pilgrim cd508410db [TargetLowering] Add vector BITCAST support to SimplifyDemandedVectorElts
Notably helps cleanup after legalization of vector types

Differential Revision: https://reviews.llvm.org/D43674

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326838 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 22:32:01 +00:00
Sebastian Pop 95e5d37d58 DA: remove uses of GEP, only ask SCEV
It's been quite some time the Dependence Analysis (DA) is broken,
as it uses the GEP representation to "identify" multi-dimensional arrays.
It even wrongly detects multi-dimensional arrays in single nested loops:

from test/Analysis/DependenceAnalysis/Coupled.ll, example @couple6
;; for (long int i = 0; i < 50; i++) {
;; A[i][3*i - 6] = i;
;; *B++ = A[i][i];

DA used to detect two subscripts, which makes no sense in the LLVM IR
or in C/C++ semantics, as there are no guarantees as in Fortran of
subscripts not overlapping into a next array dimension:

maximum nesting levels = 1
SrcPtrSCEV = %A
DstPtrSCEV = %A
using GEPs
subscript 0
    src = {0,+,1}<nuw><nsw><%for.body>
    dst = {0,+,1}<nuw><nsw><%for.body>
    class = 1
    loops = {1}
subscript 1
    src = {-6,+,3}<nsw><%for.body>
    dst = {0,+,1}<nuw><nsw><%for.body>
    class = 1
    loops = {1}
Separable = {}
Coupled = {1}

With the current patch, DA will correctly work on only one dimension:

maximum nesting levels = 1
SrcSCEV = {(-2424 + %A)<nsw>,+,1212}<%for.body>
DstSCEV = {%A,+,404}<%for.body>
subscript 0
    src = {(-2424 + %A)<nsw>,+,1212}<%for.body>
    dst = {%A,+,404}<%for.body>
    class = 1
    loops = {1}
Separable = {0}
Coupled = {}

This change removes all uses of GEP from DA, and we now only rely
on the SCEV representation.

The patch does not turn on -da-delinearize by default, and so the DA analysis
will be more conservative in the case of multi-dimensional memory accesses in
nested loops.

I disabled some interchange tests, as the DA is not able to disambiguate
the dependence anymore. To make DA stronger, we may need to
compute a bound on the number of iterations based on the access functions
and array dimensions.

The patch cleans up all the CHECKs in test/Transforms/LoopInterchange/*.ll to
avoid checking for snippets of LLVM IR: this form of checking is very hard to
maintain. Instead, we now check for output of the pass that are more meaningful
than dozens of lines of LLVM IR. Some tests now require -debug messages and thus
only enabled with asserts.

Patch written by Sebastian Pop and Aditya Kumar.

Differential Revision: https://reviews.llvm.org/D35430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326837 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 21:55:59 +00:00
Daniel Sanders e4e32bbd5b PrintStatistics() and PrintStatisticsJSON() should take StatLock
These two functions iterate over the list of statistics but don't take the lock
that protects the iterators from being invalidated by
StatisticInfo::addStatistic().

So far, this hasn't been an issue since (in-tree at least) these functions are
called by the StatisticInfo destructor so addStatistic() shouldn't be called
anymore. However, we do expose them in the public API.

Note that this only protects against iterator invalidation and does not protect
against ordering issues caused by statistic updates that race with
PrintStatistics()/PrintStatisticsJSON().

Thanks to Roman Tereshin for spotting it



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326834 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 21:16:42 +00:00
Craig Topper 2b8042c2ab [TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVectorOps to DAGCombiner::isAfterLegalizeDAG since that's what it checks. NFC
The code checks Level == AfterLegalizeDAG which is the fourth and last of the possible DAG combine stages that we have.

There is a Level called AfterLegalVectorOps, but that's the third DAG combine and it doesn't always run.

A function called isAfterLegalVectorOps should imply it returns true in either of the DAG combines that runs after the legalize vector ops stage, but that's not what this function does.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326832 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 19:44:52 +00:00
Aaron Smith 04fcfb94ad [SymboleFilePDB] Put the test input back that my previous commit clobbered
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326831 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 19:36:17 +00:00
Krzysztof Parzyszek 3459520e80 [Hexagon] Update more testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326830 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 19:15:58 +00:00
Krzysztof Parzyszek 195a164675 [Hexagon] Remove {{ *}} from testcases
The spaces in the instructions are now consistent.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326829 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 19:07:21 +00:00
Sanjay Patel a05c22c9e8 [InstCombine] simplify min/max canonicalization; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326828 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 19:01:18 +00:00
Craig Topper 6a7d6881f0 [X86] Reject registers that require a REX prefix in inline asm constraints in 32-bit mode
We don't currently reject r8-r15 or xmm8-32 or bpl/spl/sil/dil in 32-bit mode.

Differential Revision: https://reviews.llvm.org/D44031

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326826 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 18:56:33 +00:00
Stanislav Mekhanoshin 0dc2b94c4e [AMDGPU] Add default ISA version targets
In case if -mattr used to modify feature set bits in llvm-mc call
getIsaVersion can fail to identify specific ISA due to test mismatch.
Adding default fallback tests which will always correctly report at
least major version.

Differential Revision: https://reviews.llvm.org/D44163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326825 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 18:33:55 +00:00
Aaron Smith 9ac1b3521a [CodeView] Emit UdtSourceLine information for enums
Summary:
- Emit UdtSourceLine information for enums to match MSVC

- Add a method to add UDTSrcLine and call it for all Class/Struct/Union/Enum

- Update test cases to verify the changes

Reviewers: zturner, llvm-commits, rnk

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D44116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326824 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 18:20:22 +00:00
Sanjay Patel c63c5c660f [PatternMatch] define m_Not using m_Xor and cst_pred_ty
Using cst_pred_ty in the definition allows us to match vectors with undef elements.

This is a continuation of an effort to make all pattern matchers allow undef elements in vectors:
rL325437
rL325466
D43792

Differential Revision: https://reviews.llvm.org/D44076


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326823 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 18:19:42 +00:00
Rafael Espindola da57ded77c Refactor check for dllimport in the Verifier.
This avoids duplicated code and now also rejects dllimport aliases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326814 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 17:19:23 +00:00
Sanjay Patel 3c992c643c [ValueTracking] move helpers for SelectPatterns from InstCombine to ValueTracking
Most of the folds based on SelectPatternResult belong in InstSimplify rather than
InstCombine, so the helper code should be available to other passes/analysis.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326812 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 16:57:55 +00:00
Sebastian Pop b3f3c6b474 [AArch64] define isExtractSubvectorCheap
Following the ARM-neon backend, define isExtractSubvectorCheap to return true
when extracting low and high part of a neon register.

The patch disables a test in llvm/test/CodeGen/AArch64/arm64-ext.ll This
testcase is fragile in the sense that it requires a BUILD_VECTOR to "survive"
all DAG transforms until ISelLowering. The testcase is supposed to check that
AArch64TargetLowering::ReconstructShuffle() works, and for that we need a
BUILD_VECTOR in ISelLowering. As we now transform the BUILD_VECTOR earlier into
an VEXT + vector_shuffle, we don't have the BUILD_VECTOR pattern when we get to
ISelLowering. As there is no way to disable the combiner to only exercise the
code in ISelLowering, the patch disables the testcase.

Differential revision: https://reviews.llvm.org/D43973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326811 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 16:54:55 +00:00
Oliver Stannard 193fdf6730 [Asm] Fix another layering violation in assmebly macro dumping
AsmToken is in the MCParser library, so we can't use its dump function from
MCAsmMacro in the MC library. Instead, just print the string, which we don't
need the MCParser library for.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326810 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 16:51:17 +00:00
Roorda, Jan-Willem 751bada62c [Pipeliner] Test commit: fixed spelling mistake in comments
Reviewers: bcahoon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D44152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326808 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 16:26:01 +00:00
Yaxun Liu 2d74623e2e [AMDGPU] Fix lowering OpenCL enqueue_kernel
One addrspacecast disappeared in clang emitted IR for
block invoke function due to adoption of the new
addr space mapping.

Differential Revision: https://reviews.llvm.org/D43785


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326806 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 16:04:39 +00:00
Oliver Stannard fc942931a4 [ARM][Asm] Fix layering violation introduced by r326795
The MCAsmMacro::dump function is in the MCParser library, so can't be called
from the MC library.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326804 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 15:32:34 +00:00
Simi Pallipurath 0cf7d296a2 [ARM]Decoding MSR with unpredictable destination register causes an assert
This patch handling:

    Enable parsing of raw encodings of system registers .
    Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
    Disassemble msr/mrs with unpredictable sysregs as SoftFail.
    Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

Differential revision:https://reviews.llvm.org/D43374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326803 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 15:21:19 +00:00
Simi Pallipurath 2a9d5b1b03 test commit: fix typo in comment
This is  a simple change to do the test commit and verify commit access.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326800 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 14:35:23 +00:00
Oliver Stannard 2fb672c0b9 [Asm] Add debug printing for assembler macros
This adds some debug printing (gated behind the "asm-macros" debug flag) which
can help tracing complicated assembly macros.

Differential revision: https://reviews.llvm.org/D43937



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326795 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 14:07:01 +00:00
Oliver Stannard 3c24f8abd8 [Asm] Refactor debug printing of AsmToken
* Move printing from llvm-mc to the AsmToken class, so that it can be used elsewhere.
* Add 5 cases which were missed: BigNum, Comment, HashDirective, Space and
  BackSlash, and remove the default case so that -Wswitch will catch this error
  in future.

This is almost NFC, except for the fact that llvm-mc can now print those 5
tokens in -as-lex mode.

Differential revision: https://reviews.llvm.org/D43936



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326794 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 14:02:14 +00:00
Florian Hahn dc7756a32c [CallSiteSplitting] Do not crash when BB's terminator changes.
Change doCallSiteSplitting to iterate until we reach the terminator instruction.
tryToSplitCallSite can replace BB's terminator in case BB is a successor of
itself. Then IE will be invalidated and we also have to check the current
terminator.

Reviewers: junbuml, davidxl, davide, fhahn

Reviewed By: fhahn, junbuml

Differential Revision: https://reviews.llvm.org/D43824


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326793 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 14:00:58 +00:00
Nicolai Haehnle 8498a493c8 TableGen: Add !foldl operation
Change-Id: I63d67bf6e0b315e2d3360e47e3b62c9517f38987

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326790 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:49:16 +00:00
Nicolai Haehnle 33774b4ded TableGen: Remove the ResolveFirst mechanism
Summary:
It is no longer used.

Change-Id: I1e47267d1975d43ad43acd6347f54e958e3b6c86

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43757

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326789 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:49:06 +00:00
Nicolai Haehnle 1f3e2338d9 TableGen: Delay instantiating inline anonymous records
Summary:
Only instantiate anonymous records once all variable references in template
arguments have been resolved. This allows patterns like the new test case,
which in practice can appear in expressions like:

  class IntrinsicTypeProfile<list<LLVMType> ty, int shift> {
    list<LLVMType> types =
      !listconcat(ty, [llvm_any_ty, LLVMMatchType<shift>]);
  }

  class FooIntrinsic<IntrinsicTypeProfile P, ...>
    : Intrinsic<..., P.types, ...>;

Without this change, the anonymous LLVMMatchType instantiation would
never get resolved.

Another consequence of this change is that anonymous inline
instantiations are uniqued via the folding set of the newly introduced
VarDefInit.

Change-Id: I7a7041a20e297cf98c9109b28d85e64e176c932a

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43756

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326788 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:49:01 +00:00
Nicolai Haehnle ea80ae41c7 TableGen: Move getNewAnonymousName into RecordKeeper
Summary:
So that we will be able to generate new anonymous names more easily
outside the parser as well.

Change-Id: I28f396a7bdbc3ff0c665d466abbd3d31376e21b4

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43755

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326787 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:48:54 +00:00
Nicolai Haehnle 19ebaa70e5 TableGen: Explicitly check whether a record has been resolved
Summary:
There are various places where resolving and constant folds can
get stuck, especially around casts. We don't always signal an
error for those, because in many cases they can legitimately
occur without being an error in the "untaken branch" of an !if.

Change-Id: I3befc0e4234c8e6cc61190504702918c9f29ce5c

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43754

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326786 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:48:47 +00:00
Nicolai Haehnle a9e8c1d609 TableGen: Allow !cast of records, cleanup conversion machinery
Summary:
Distinguish two relationships between types: is-a and convertible-to.
For example, a bit is not an int or vice versa, but they can be
converted into each other (with range checks that you can think of
as "dynamic": unlike other type checks, those range checks do not
happen during parsing, but only once the final values have been
established).

Actually converting initializers between types is subtle: even
when values of type A can be converted to type B (e.g. int into
string), it may not be possible to do so with a concrete initializer
(e.g., a VarInit that refers to a variable of type int cannot
be immediately converted to a string).

For this reason, distinguish between getCastTo and convertInitializerTo:
the latter implements the actual conversion when appropriate, while
the former will first try to do the actual conversion and fall back
to introducing a !cast operation so that the conversion will be
delayed until variable references have been resolved.

To make the approach of adding !cast operations to work, !cast needs
to fallback to convertInitializerTo when the special string <-> record
logic does not apply.

This enables casting records to a subclass, although that new
functionality is only truly useful together with !isa, which will be
added in a later change.

The test is removed because it uses !srl on a bit sequence,
which cannot really be supported consistently, but luckily
isn't used anywhere either.

Change-Id: I98168bf52649176654ed2ec61a29bdb29970cfe7

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43753

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326785 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:48:39 +00:00
Nicolai Haehnle c1b25e6856 TableGen: Simplify BitsInit::resolveReferences
Summary:
No functional change intended. The removed code has a loop for
recursive resolving, which is superseded by the recursive
resolving done by the Resolver implementations.

Add a test case which was broken by an earlier version of this
change.

Change-Id: Ib208d037b77a8bbb725977f1388601fc984723d8

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43655

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326784 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:48:30 +00:00
Nicolai Haehnle c1dad06968 TableGen: Generalize record types to fix typeIsConvertibleTo et al.
Summary:
Allow RecordRecTy to represent the type "subclass of N superclasses",
where N may be zero. Furthermore, generate RecordRecTy instances only
with actual classes in the list.

Keeping track of multiple superclasses is required to resolve the type
of a list correctly in some cases. The old code relied on the incorrect
behavior of typeIsConvertibleTo, and an earlier version of this change
relied on a modified ordering of superclasses (it was committed in
r325884 and then reverted because unfortunately some of clang-tblgen's
backends depend on the ordering).

Previously, the DefInit for each Record would have a RecordRecTy of
that Record as its type. Now, all defs with the same superclasses will
share the same type.

This allows us to be more consistent about type checks involving records:

- typeIsConvertibleTo actually requires the LHS to be a subtype of the
  RHS

- resolveTypes will return the least supertype of given record types in
  all cases

- different record types in the two branches of an !if are handled
  correctly

Add a test that used to be accepted without flagging the obvious type
error.

Change-Id: Ib366db1a4e6a079f1a0851e469b402cddae76714

Reviewers: arsenm, craig.topper, tra, MartinO

Subscribers: wdng, llvm-commits

Differential Revision: https://reviews.llvm.org/D43680

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326783 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:48:20 +00:00
Bjorn Pettersson 866cf8f3af Fixup for rL326769 (RegState::Debug is being truncated to a bool)
I obviously messed up arguments to MachineOperand::CreateReg
in rL326769. This should make it work as intended.

Thanks to RKSimon for spotting this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326780 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:23:28 +00:00
Florian Hahn 6fdde843d6 [CloneFunction] Support BB == PredBB in DuplicateInstructionsInSplit.
In case PredBB == BB and StopAt == BB's terminator, StopAt != &*BI will
fail, because BB's terminator instruction gets replaced.

By using BB.getTerminator() we get the current terminator which we can use
to compare.

Reviewers: sanjoy, anna, reames

Reviewed By: anna

Differential Revision: https://reviews.llvm.org/D43822


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326779 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 13:12:32 +00:00
Dylan McKay d45c0f1adf [AVR] Remove the earlyclobber flag from LDDWRdYQ
Before I started maintaining the AVR backend, this instruction
never originally used to have an earlyclobber flag.

Some time afterwards (years ago), I must've added it back in, not realising that it
was left out for a reason.

This pseudo instrction exists solely to work around a long standing bug
in the register allocator.

Before this commit, the LDDWRdYQ pseudo was not actually working around
any bug. With the earlyclobber flag removed again, the LDDWRdYQ pseudo
now correctly works around PR13375 again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326774 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 11:20:25 +00:00
Bjorn Pettersson 783006ec19 [DebugInfo] Discard invalid DBG_VALUE instructions in LiveDebugVariables
Summary:
This is a workaround for pr36417
https://bugs.llvm.org/show_bug.cgi?id=36417

LiveDebugVariables will now verify that the DBG_VALUE instructions
are sane (prior to register allocation) by asking LIS if a virtual
register used in the DBG_VALUE is live (or dead def) in the slot
index before the DBG_VALUE. If it isn't sane the DBG_VALUE is
discarded.

One pass that was identified as introducing non-sane DBG_VALUE
instructtons, when analysing pr36417, was the DAG->DAG Instruction
Selection. It sometimes inserts DBG_VALUE instructions referring to
a virtual register that is defined later in the same basic block.
So it is a use before def kind of problem. The DBG_VALUE is
typically inserted in the beginning of a basic block when this
happens. The problem can be seen in the test case
test/DebugInfo/X86/dbg-value-inlined-parameter.ll

Reviewers: aprantl, rnk, probinson

Reviewed By: aprantl

Subscribers: vsk, davide, alexcrichton, Ka-Ka, eraman, llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D43956

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326769 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 08:47:07 +00:00
Sam Clegg 068c05aeb4 [WebAssebmly] Remove reloc ordering constraint
The MC layer doesn't currently emit relocations in offset
order for the entire code section so this check was causing
failures on the wasm waterfall.

Perhaps we can re-instate this check if we divide the relocations
per-function, or add extra ordering the MC object writer.

Differential Revision: https://reviews.llvm.org/D44136

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326765 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 07:13:10 +00:00
Martin Storsjo ea4dd0b919 [X86] Handle EAX being live when calling chkstk for x86_64
EAX can turn out to be alive here, when shrink wrapping is done
(which is allowed when using dwarf exceptions, contrary to the
normal case with WinCFI).

This fixes PR36487.

Differential Revision: https://reviews.llvm.org/D43968

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326764 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 06:00:13 +00:00
Serge Pavlov 6dbdbdd86a Updated docs in CrashRecoveryContext.h
Differential Revision: https://reviews.llvm.org/D43200


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326763 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 04:00:30 +00:00
Paul Robinson bc32224980 Revert "[DWARFv5] Emit file 0 to the line table."
Caused an asan failure.

This reverts commit d54883f081186cdcce74e6f98cfc0438579ec019.
aka r326758

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326762 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 03:15:21 +00:00
Xin Tong 434547e0c5 [MergeICmp] Simplify how BCECmpBlock instructions are blacklisted
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326761 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 02:24:02 +00:00
Xin Tong 806f65e3f5 [MergeICmp] Fix printing. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326760 91177308-0d34-0410-b5e6-96231b3b80d8
2018-03-06 02:04:57 +00:00