Commit Graph

1879 Commits

Author SHA1 Message Date
Philip Reames 27daa20eac Update -analyze -scalar-evolution output for multiple exit loops w/computable exit values
The previous output was next to useless if *any* exit was not computable.  If we have more than one exit, show the exit count for each so that it's easier to see what's going from with SCEV analysis when debugging.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364579 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 19:22:43 +00:00
Roland Froese d3e9a826c5 Recommit [PowerPC] Update P9 vector costs for insert/extract element
Recommit patch D60160 after regression fix patch D63463.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364557 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-27 16:20:24 +00:00
Florian Hahn cc3c3219a7 [LoopUnroll] Add support for loops with exiting headers and uncond latches.
This patch generalizes the UnrollLoop utility to support loops that exit
from the header instead of the latch. Usually, LoopRotate would take care
of must of those cases, but in some cases (e.g. -Oz), LoopRotate does
not kick in.

Codesize impact looks relatively neutral on ARM64 with -Oz + LTO.

Program                                         master     patch     diff
 External/S.../CFP2006/447.dealII/447.dealII   629060.00  627676.00  -0.2%
 External/SPEC/CINT2000/176.gcc/176.gcc        1245916.00 1244932.00 -0.1%
 MultiSourc...Prolangs-C/simulator/simulator   86100.00   86156.00    0.1%
 MultiSourc...arks/Rodinia/backprop/backprop   66212.00   66252.00    0.1%
 MultiSourc...chmarks/Prolangs-C++/life/life   67276.00   67312.00    0.1%
 MultiSourc...s/Prolangs-C/compiler/compiler   69824.00   69788.00   -0.1%
 MultiSourc...Prolangs-C/assembler/assembler   86672.00   86696.00    0.0%

Reviewers: efriedma, vsk, paquette

Reviewed By: paquette

Differential Revision: https://reviews.llvm.org/D61962

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364398 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-26 09:16:57 +00:00
Yevgeny Rouban c49d7cf3b1 [LICM & MSSA] Fixed test to run only with assertions enabled as it uses -debug-only
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364005 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-21 04:49:40 +00:00
Alina Sbirlea 3ad1311a81 [LICM & MSSA] Limit unsafe sinking and hoisting.
Summary:
The getClobberingMemoryAccess API checks for clobbering accesses in a loop by walking the backedge. This may check if a memory access is being
clobbered by the loop in a previous iteration, depending how smart AA got over the course of the updates in MemorySSA (it does not occur when built from scratch).
If no clobbering access is found inside the loop, it will optimize to an access outside the loop. This however does not mean that access is safe to sink.
Given:
```
for i
  load a[i]
  store a[i]
```
The access corresponding to the load can be optimized to outside the loop, and the load can be hoisted. But it is incorrect to sink it.
In order to sink the load, we'd need to check no Def clobbers the Use in the same iteration. With this patch we currently restrict sinking to either
Defs not existing in the loop, or Defs preceding the load in the same block. An easy extension is to ensure the load (Use) post-dominates all Defs.

Caught by PR42294.

This issue also shed light on the converse problem: hoisting stores in this same scenario would be illegal. With this patch we restrict
hoisting of stores to the case when their corresponding Defs are dominating all Uses in the loop.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63582

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363982 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-20 21:09:09 +00:00
Alina Sbirlea 2081dbcd9b [MemorySSA] Cleanup trivial phis.
Summary:
This is unfortunately needed for correctness, if we are to extend the tolerance of the update API to the way simple loop unswitch is doing cloning.

In simple loop unswitch (as opposed to loop unswitch), not all blocks are cloned. This can create unreachable cloned blocks (no predecessor), which are later cleaned up.

In MemorySSA, the  APIs for supporting these kind of updates (clone + update exit blocks), make certain assumption on the integrity of the CFG. When cloning, if something was not cloned, it's values in MemorySSA default to LiveOnEntry. When updating exit blocks, it is safe to assume that we can first insert phis in the blocks merging two clones, then add additional phis in the IDF of the blocks that received phis. This no longer holds true if one of the clones being merged comes from an unreachable block. We'd conservatively need to add all phis before filling in their incoming definitions. In practice this restriction can be relaxed if we clean up trivial phis after the first round of insertion.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363880 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-19 21:33:09 +00:00
Bjorn Pettersson f99e13e425 [ConstantFolding] Add constant folding for smul.fix and smul.fix.sat
Summary:
This patch teaches ConstantFolding to constant fold
both scalar and vector variants of llvm.smul.fix and
llvm.smul.fix.sat.

As described in the LangRef rounding is unspecified for
these instrinsics. If the result cannot be represented
exactly the default behavior in ConstantFolding is to
round down towards negative infinity. If a target has a
preferred rounding that is different some kind of target
hook would be needed (same strategy as used by the
SelectionDAG legalizer).

Reviewers: nikic, leonardchan, RKSimon

Reviewed By: leonardchan

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63385

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363811 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-19 14:28:03 +00:00
Alina Sbirlea 6327268c4c [MemorySSA] Don't use template when the clone is a simplified instruction.
Summary:
LoopRotate doesn't create a faithful clone of an instruction, it may
simplify it beforehand. Hence the clone of an instruction that has a
MemoryDef associated may not be a definition, but a use or not a memory
alternig instruction.
Don't rely on the template when the clone may be simplified.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63355

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363597 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-17 18:58:40 +00:00
Alina Sbirlea e0ff6cd963 [MemorySSA] Add all MemoryPhis before filling their values.
Summary:
Add all MemoryPhis in IDF before filling in their incomign values.
Otherwise, a new Phi can be added that needs to become the incoming
value of another Phi.
Test fails the verification in verifyPrevDefInPhis.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, zzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63353

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363590 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-17 18:16:53 +00:00
Fangrui Song 1002960b9d [lit] Delete empty lines at the end of lit.local.cfg NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363538 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-17 09:51:07 +00:00
Nikita Popov b435405a04 [SCEV] Use unsigned/signed intersection type in SCEV
Based on D59959, this switches SCEV to use unsigned/signed range
intersection based on the sign hint. This will prefer non-wrapping
ranges in the relevant domain. I've left the one intersection in
getRangeForAffineAR() to use the smallest intersection heuristic,
as there doesn't seem to be any obvious preference there.

Differential Revision: https://reviews.llvm.org/D60035

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363490 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-15 09:15:52 +00:00
Stanislav Mekhanoshin 3ff2fb8887 [AMDGPU] ImmArg and SourceOfDivergence for permlane/dpp
Added missing ImmArg and SourceOfDivergence to the crosslane
intrinsics.

Differential Revision: https://reviews.llvm.org/D63216

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363276 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-13 16:31:51 +00:00
Sander de Smalen cdca5bb4d5 Improve reduction intrinsics by overloading result value.
This patch uses the mechanism from D62995 to strengthen the
definitions of the reduction intrinsics by letting the scalar
result/accumulator type be overloaded from the vector element type.

For example:

  ; The LLVM LangRef specifies that the scalar result must equal the
  ; vector element type, but this is not checked/enforced by LLVM.
  declare i32 @llvm.experimental.vector.reduce.or.i32.v4i32(<4 x i32> %a)

This patch changes that into:

  declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a)

Which has the type-constraint more explicit and causes LLVM to check
the result type with the vector element type.

Reviewers: RKSimon, arsenm, rnk, greened, aemerson

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D62996


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363240 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-13 09:37:38 +00:00
Matt Arsenault 4d8041c0e5 LoopDistribute/LAA: Respect convergent
This case is slightly tricky, because loop distribution should be
allowed in some cases, and not others. As long as runtime dependency
checks don't need to be introduced, this should be OK. This is further
complicated by the fact that LoopDistribute partially ignores if LAA
says that vectorization is safe, and then does its own runtime pointer
legality checks.

Note this pass still does not handle noduplicate correctly, as this
should always be forbidden with it. I'm not going to bother trying to
fix it, as it would require more effort and I think noduplicate should
be removed.

https://reviews.llvm.org/D62607

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363160 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-12 13:34:19 +00:00
Alina Sbirlea 68e99ab974 [MemorySSA] When applying updates, clean unnecessary Phis.
Summary: After applying a set of insert updates, there may be trivial Phis left over. Clean them up.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63033

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363094 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-11 19:09:34 +00:00
Whitney Tsang b1c4b0155f [DA] Add an option to control delinearization validity checks
Summary: Dependence Analysis performs static checks to confirm validity
of delinearization. These checks often fail for 64-bit targets due to
type conversions and integer wrapping that prevent simplification of the
SCEV expressions. These checks would also fail at compile-time if the
lower bound of the loops are compile-time unknown.
Author: bmahjour
Reviewer: Meinersbur, jdoerfert, kbarton, dmgreen, fhahn
Reviewed By: Meinersbur, jdoerfert, dmgreen
Subscribers: fhahn, hiraditya, javed.absar, llvm-commits, Whitney,
etiotto
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D62610

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362952 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-10 15:29:07 +00:00
David Green 0f4acbbf40 [ARM] Adjust isLegalT1AddressImmediate for non-legal types
Types such as float and i64's do not have legal loads in Thumb1, but will still
be loaded with a LDR (or potentially multiple LDR's). As such we can treat the
cost of addressing mode calculations the same as an i32 and get some optimisation
benefits.

Differential Revision: https://reviews.llvm.org/D62968


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362874 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-08 10:32:53 +00:00
David Green f62bbb6909 [ARM] Add MVE addressing to isLegalT2AddressImmediate
Now with MVE being added, we can add the vector addressing mode costs for it.
These are generally imm7 multiplied by the size of the type being loaded /
stored.

Differential Revision: https://reviews.llvm.org/D62967


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362873 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-08 10:18:23 +00:00
David Green 3ca35d81c1 [ARM] Add fp16 addressing to isLegalT2AddressImmediate
The fp16 version of VLDR takes a imm8 multiplied by 2. This updates the costs
to account for those, and adds extra testing. It is dependant upon hasFPRegs16
as this is what the load/store instructions require.

Differential Revision: https://reviews.llvm.org/D62966


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362872 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-08 10:09:02 +00:00
David Green 516565caaf [ARM] Add extra gep costmodel tests for MVE and half float. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362871 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-08 09:58:05 +00:00
Craig Topper fe02c270b5 [CFLGraph] Add support for unary fneg instruction.
Differential Revision: https://reviews.llvm.org/D62791

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362737 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-06 19:21:23 +00:00
Luis Marques 5684d0845b [RISCV] Disable test/Analysis/CostModel/RISCV tests if RISCV backend not built
Adds missing lit.local.cfg. Fixes rL362691.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362693 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-06 10:12:28 +00:00
Luis Marques 5529d774dd [RISCV] Add CostModel GEP tests
Differential Revision: https://reviews.llvm.org/D61185


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362691 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-06 09:47:53 +00:00
Matt Arsenault a69b8271d5 TTI: Improve default costs for addrspacecast
For some reason multiple places need to do this, and the variant the
loop unroller and inliner use was not handling it.

Also, introduce a new wrapper to be slightly more precise, since on
AMDGPU some addrspacecasts are free, but not no-ops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362436 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-03 18:41:34 +00:00
Simon Pilgrim 3748537115 [CostModel][X86] Improve masked load/store AVX1/AVX2 costs
A mixture of internal tests and review of the scheduler models indicates we're overestimating the cost of a masked load, which we're estimating at 4x regular memory ops - more realistic values indicates that its closer to 2x. Masked stores costs are a lot more diverse but 8x is roughly in the middle of the range.

e.g. SandyBridge
defm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>;
defm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>;
defm : X86WriteRes<WriteFMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
defm : X86WriteRes<WriteFMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;

e.g. Btver2
defm : X86WriteRes<WriteFMaskedLoad, [JLAGU, JFPU01, JFPX], 6, [1, 2, 2], 1>;
defm : X86WriteRes<WriteFMaskedLoadY, [JLAGU, JFPU01, JFPX], 6, [2, 4, 4], 2>;
defm : X86WriteRes<WriteFMaskedStore, [JSAGU, JFPU01, JFPX], 6, [1, 1, 4], 1>;
defm : X86WriteRes<WriteFMaskedStoreY, [JSAGU, JFPU01, JFPX], 6, [2, 2, 4], 2>;

Differential Revision: https://reviews.llvm.org/D61257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362338 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-02 20:37:02 +00:00
Simon Pilgrim fe525772da [CostModel][X86] Add bool vector and/or/xor cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362083 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-30 10:41:04 +00:00
Craig Topper 315a86c2f2 [CostModel] Add really basic support for being able to query the cost of the FNeg instruction.
Summary:
This reuses the getArithmeticInstrCost, but passes dummy values of the second
operand flags.

The X86 costs are wrong and can be improved in a follow up. I just wanted to
stop it from reporting an unknown cost first.

Reviewers: RKSimon, spatel, andrew.w.kaylor, cameron.mcinally

Reviewed By: spatel

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62444

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361788 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-28 04:09:18 +00:00
Xing Xue 7e46dce0de [MustExecute] Improve MustExecute to correctly handle loop nest
Summary:
for.outer:
  br for.inner
for.inner:
  LI <loop invariant load instruction>
for.inner.latch:
  br for.inner, for.outer.latch
for.outer.latch:
  br for.outer, for.outer.exit

LI is a loop invariant load instruction that post dominate for.outer, so LI should be able to move out of the loop nest. However, there is a bug in allLoopPathsLeadToBlock().

Current algorithm of allLoopPathsLeadToBlock()

  1. get all the transitive predecessors of the basic block LI belongs to (for.inner) ==> for.outer, for.inner.latch
  2. if any successors of any of the predecessors are not for.inner or for.inner's predecessors, then return false
  3. return true

Although for.inner.latch is for.inner's predecessor, but for.inner dominates for.inner.latch, which means if for.inner.latch is ever executed, for.inner should be as well. It should not return false for cases like this.

Author: Whitney (committed by xingxue)

Reviewers: kbarton, jdoerfert, Meinersbur, hfinkel, fhahn

Reviewed By: jdoerfert

Subscribers: hiraditya, jsji, llvm-commits, etiotto, bmahjour

Tags: #LLVM

Differential Revision: https://reviews.llvm.org/D62418

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361762 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-27 13:57:28 +00:00
Craig Topper c673564596 [X86] Add test cases for D62444. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361745 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-27 05:27:57 +00:00
David Bolvansky 92ce94fff3 [SimplifyCFG] Added condition assumption for unreachable blocks
Summary: PR41688

Reviewers: spatel, efriedma, craig.topper, hfinkel, reames

Reviewed By: hfinkel

Subscribers: javed.absar, dmgreen, fhahn, hfinkel, reames, nikic, lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61409

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361707 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-25 22:34:27 +00:00
David Bolvansky f441bf782f [NFC] Update test checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361695 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-25 13:11:22 +00:00
Jonas Paulsson 1af13e6948 [CodeMetrics] Don't let extends of i1 be free.
getUserCost() currently returns TCC_Free for any extend of a compare (i1)
result. It seems this is only true in a limited number of cases where for
example two compares are chained. Even in those types of cases it seems
unlikely that they are generally free, while they may be in some cases.

This patch therefore removes this special handling of cast of i1. No tests
are failing because of this.

If some target want the old behavior, it could override getUserCost().

Review: Hal Finkel, Chandler Carruth, Evgeny Astigeevich, Simon Pilgrim,
        Ulrich Weigand
https://reviews.llvm.org/D54742/new/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360970 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-17 01:26:35 +00:00
Alina Sbirlea 9a5c1fd7a9 [MemorySSA] LoopSimplify preserves MemorySSA only when flag is flipped.
LoopSimplify can preserve MemorySSA after r360270.
But the MemorySSA analysis is retrieved and preserved only when the
EnableMSSALoopDependency is set to true. Use the same conditional to
mark the pass as preserved, otherwise subsequent passes will get an
invalid analysis.
Resolves PR41853.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360697 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-14 18:07:18 +00:00
Simon Pilgrim ab39cf6afa [CostModel][X86] Add min/max reduction costs for all SSE targets
The original costs stopped at SSE42, I've added conservative estimates for everything down to SSE1/SSE2 and moved some of the SSE42 costs to SSE41 (really only the addition of PCMPGT makes any difference).

I've also added missing vXi8 costs (we use PHMINPOSUW for i8/i16 for scarily quick results) and 256-bit vector costs for AVX1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360528 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-11 17:12:52 +00:00
Alina Sbirlea 6138d24766 [MemorySSA] Fix CHECKs in test. [NFC]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360201 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-07 22:26:52 +00:00
Keno Fischer 35a5cc8b49 [SCEV] Add explicit representations of umin/smin
Summary:
Currently we express umin as `~umax(~x, ~y)`. However, this becomes
a problem for operands in non-integral pointer spaces, because `~x`
is not something we can compute for `x` non-integral. However, since
comparisons are generally still allowed, we are actually able to
express `umin(x, y)` directly as long as we don't try to express is
as a umax. Support this by adding an explicit umin/smin representation
to SCEV. We do this by factoring the existing getUMax/getSMax functions
into a new function that does all four. The previous two functions were
largely identical.

Reviewed By: sanjoy
Differential Revision: https://reviews.llvm.org/D50167

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360159 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-07 15:28:47 +00:00
Cameron McInally a0a00583bd Add FNeg support to InstructionSimplify
Differential Revision: https://reviews.llvm.org/D61573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360053 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-06 16:05:10 +00:00
Cameron McInally d16e056172 Precommit an FNeg InstructionSimplify test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359990 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-05 18:22:09 +00:00
Cameron McInally ed1ec3ab25 Add FNeg IR constant folding support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359982 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-05 16:07:09 +00:00
Alina Sbirlea 15bfdc5aa5 [MemorySSA] Check that block is reachable when adding phis.
Summary:
Originally the insertDef method was only used when building MemorySSA, and was limiting the number of Phi nodes that it created.
Now it's used for updates as well, and it can create additional Phis needed for correctness.
Make sure no Phis are created in unreachable blocks (condition met during MSSA build), otherwise the renamePass will find a null DTNode.

Resolves PR41640.

Reviewers: george.burgess.iv

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61410

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359845 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-02 23:41:58 +00:00
David L. Jones 9697ae39f6 Revert "[llvm] r359313 - [PowerPC] Update P9 vector costs for insert/extract element"
This causes segfaults during optimized builds. More details, including a reproducer, are on the llvm-commits thread for r359313.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359648 91177308-0d34-0410-b5e6-96231b3b80d8
2019-05-01 05:01:03 +00:00
Alina Sbirlea c049743f98 [MemorySSA] Invalidate MemorySSA if AA or DT are invalidated.
Summary:
MemorySSA keeps internal pointers of AA and DT.
If these get invalidated, so should MemorySSA.

Reviewers: george.burgess.iv, chandlerc

Subscribers: jlebar, Prazek, llvm-commits

Tags: LLVM

Differential Revision: https://reviews.llvm.org/D61043

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359627 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-30 22:43:55 +00:00
Alina Sbirlea ddcc2ba101 [AliasAnalysis/NewPassManager] Invalidate AAManager less often.
Summary:
This is a redo of D60914.

The objective is to not invalidate AAManager, which is stateless, unless
there is an explicit invalidate in one of the AAResults.

To achieve this, this patch adds an API to PAC, to check precisely this:
is this analysis not invalidated explicitly == is this analysis not abandoned == is this analysis stateless, so preserved without explicitly being marked as preserved by everyone

Reviewers: chandlerc

Subscribers: mehdi_amini, jlebar, george.burgess.iv, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61284

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359622 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-30 22:15:47 +00:00
Simon Pilgrim 883da93f67 Revert rL359519 : [MemorySSA] Invalidate MemorySSA if AA or DT are invalidated.
Summary:
MemorySSA keeps internal pointers of AA and DT.
If these get invalidated, so should MemorySSA.

Reviewers: george.burgess.iv, chandlerc

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61043
........
This was causing windows build bot failures

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359555 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-30 12:34:21 +00:00
Sjoerd Meijer 71dbcf0b11 [ARM] Implement TTI::getMemcpyCost
This implements TargetTransformInfo method getMemcpyCost, which estimates the
number of instructions to which a memcpy instruction expands to.

Differential Revision: https://reviews.llvm.org/D59787


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359547 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-30 10:28:50 +00:00
Alina Sbirlea a47aa18633 [MemorySSA] Invalidate MemorySSA if AA or DT are invalidated.
Summary:
MemorySSA keeps internal pointers of AA and DT.
If these get invalidated, so should MemorySSA.

Reviewers: george.burgess.iv, chandlerc

Subscribers: jlebar, Prazek, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61043

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359519 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-29 23:53:04 +00:00
Roland Froese 61c6064699 [PowerPC] Update P9 vector costs for insert/extract element
The PPC vector cost model values for insert/extract element reflect older
processors that lacked vector insert/extract and move-to/move-from VSR
instructions.  Update getVectorInstrCost to give appropriate values for when
the newer instructions are present.

Differential Revision: https://reviews.llvm.org/D60160


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359313 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-26 16:14:17 +00:00
Alina Sbirlea 20b802a025 Revert [AliasAnalysis] AAResults preserves AAManager.
Triggers use-after-free.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359055 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-24 00:28:29 +00:00
Josh Stone 07bbdf4564 [Lint] Permit aliasing noalias readonly arguments
Summary:
If two arguments are both readonly, then they have no memory dependency
that would violate noalias, even if they do actually overlap.

Reviewers: hfinkel, efriedma

Reviewed By: efriedma

Subscribers: efriedma, hiraditya, llvm-commits, tstellar

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60239

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359047 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-23 23:43:47 +00:00
Alina Sbirlea c8d498d36b [AliasAnalysis] AAResults preserves AAManager.
Summary:
AAResults should not invalidate AAManager.
Update tests.

Reviewers: chandlerc

Subscribers: mehdi_amini, jlebar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60914

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359014 91177308-0d34-0410-b5e6-96231b3b80d8
2019-04-23 17:21:18 +00:00