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llvm/lib/CodeGen/SelectionDAG
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Guillaume Chatelet 0e61c30e7d [Alignment][NFC] TargetCallingConv::setByValAlign 
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69248

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375410 91177308-0d34-0410-b5e6-96231b3b80d8
2019-10-21 12:05:33 +00:00
..
CMakeLists.txt
…
DAGCombiner.cpp
[AArch64][SVE] Add SPLAT_VECTOR ISD Node
2019-10-18 11:48:35 +00:00
FastISel.cpp
[Alignment][NFC] TargetCallingConv::setByValAlign
2019-10-21 12:05:33 +00:00
FunctionLoweringInfo.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
InstrEmitter.cpp
[DebugInfo] Remove some users of DBG_VALUEs IsIndirect field
2019-10-15 10:46:24 +00:00
InstrEmitter.h
…
LegalizeDAG.cpp
Prune Analysis includes from SelectionDAG.h
2019-10-19 01:07:48 +00:00
LegalizeFloatTypes.cpp
…
LegalizeIntegerTypes.cpp
[AArch64][SVE] Add SPLAT_VECTOR ISD Node
2019-10-18 11:48:35 +00:00
LegalizeTypes.cpp
…
LegalizeTypes.h
[AArch64][SVE] Add SPLAT_VECTOR ISD Node
2019-10-18 11:48:35 +00:00
LegalizeTypesGeneric.cpp
[LegalizeTypes][X86] When splitting a vselect for type legalization, don't split a setcc condition if the setcc input is legal and vXi1 conditions are supported
2019-10-06 18:43:03 +00:00
LegalizeVectorOps.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
LegalizeVectorTypes.cpp
[LegalizeTypes] Don't use PromoteTargetBoolean in WidenVecOp_SETCC.
2019-10-16 03:29:24 +00:00
LLVMBuild.txt
…
ResourcePriorityQueue.cpp
…
ScheduleDAGFast.cpp
…
ScheduleDAGRRList.cpp
[ScheduleDAG] When a node is cloned, add an edge between the nodes.
2019-10-04 19:51:40 +00:00
ScheduleDAGSDNodes.cpp
Prune Analysis includes from SelectionDAG.h
2019-10-19 01:07:48 +00:00
ScheduleDAGSDNodes.h
Prune Analysis includes from SelectionDAG.h
2019-10-19 01:07:48 +00:00
ScheduleDAGVLIW.cpp
Prune Analysis includes from SelectionDAG.h
2019-10-19 01:07:48 +00:00
SDNodeDbgValue.h
…
SelectionDAG.cpp
[FPEnv] Add constrained intrinsics for lrint and lround
2019-10-07 13:20:00 +00:00
SelectionDAGAddressAnalysis.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
SelectionDAGBuilder.cpp
[Alignment][NFC] TargetCallingConv::setByValAlign
2019-10-21 12:05:33 +00:00
SelectionDAGBuilder.h
…
SelectionDAGDumper.cpp
[AArch64][SVE] Add SPLAT_VECTOR ISD Node
2019-10-18 11:48:35 +00:00
SelectionDAGISel.cpp
Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
2019-10-19 01:31:09 +00:00
SelectionDAGPrinter.cpp
…
SelectionDAGTargetInfo.cpp
…
StatepointLowering.cpp
…
StatepointLowering.h
…
TargetLowering.cpp
[TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2)
2019-10-19 16:57:02 +00:00