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https://github.com/RPCS3/llvm.git
synced 2026-08-26 18:26:51 -04:00
Adhemerval Zanella
eb02a3bc90
This patch optimizes ISD::LROUND and ISD::LLROUND to fcvtas instruction. It currently only handles the scalar version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360894 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
1.3 KiB
LLVM
61 lines
1.3 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
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; CHECK-LABEL: testmsws:
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; CHECK: fcvtas x0, s0
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; CHECK: ret
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define i32 @testmsws(float %x) {
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entry:
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%0 = tail call i64 @llvm.llround.f32(float %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsxs:
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; CHECK: fcvtas x0, s0
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; CHECK-NEXT: ret
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define i64 @testmsxs(float %x) {
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entry:
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%0 = tail call i64 @llvm.llround.f32(float %x)
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ret i64 %0
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}
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; CHECK-LABEL: testmswd:
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; CHECK: fcvtas x0, d0
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; CHECK: ret
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define i32 @testmswd(double %x) {
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entry:
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%0 = tail call i64 @llvm.llround.f64(double %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsxd:
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; CHECK: fcvtas x0, d0
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; CHECK-NEXT: ret
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define i64 @testmsxd(double %x) {
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entry:
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%0 = tail call i64 @llvm.llround.f64(double %x)
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ret i64 %0
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}
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; CHECK-LABEL: testmswl:
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; CHECK: bl llroundl
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define i32 @testmswl(fp128 %x) {
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entry:
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%0 = tail call i64 @llvm.llround.f128(fp128 %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsll:
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; CHECK: b llroundl
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define i64 @testmsll(fp128 %x) {
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entry:
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%0 = tail call i64 @llvm.llround.f128(fp128 %x)
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ret i64 %0
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}
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declare i64 @llvm.llround.f32(float) nounwind readnone
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declare i64 @llvm.llround.f64(double) nounwind readnone
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declare i64 @llvm.llround.f128(fp128) nounwind readnone
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