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https://github.com/RPCS3/llvm.git
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David Greene
bbd45bf0b7
Re-apply r345315 with testcase fixes. Include all of the store's source vector operands when creating the MachineMemOperand. Previously, we were missing the first operand, making the store size seem smaller than it really is. Differential Revision: https://reviews.llvm.org/D52816 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345631 91177308-0d34-0410-b5e6-96231b3b80d8
83 lines
4.0 KiB
LLVM
83 lines
4.0 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -stop-after=instruction-select < %s | FileCheck %s
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declare void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, float*)
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declare void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, i64, float*)
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declare void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float>, <4 x float>, <4 x float>, <4 x float>, i64, float*)
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define void @addstx(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST2Twov4s {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST3Threev4s {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST4Fourv4s {{.*}} :: (store 64 {{.*}})
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ret void
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}
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define void @addst1x(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st1x2.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, float* %res)
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; CHECK: ST1Twov4s {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st1x3.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, float* %res)
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; CHECK: ST1Threev4s {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st1x4.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, float* %res)
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; CHECK: ST1Fourv4s {{.*}} :: (store 64 {{.*}})
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ret void
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}
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define void @addstxlane(float* %res, <4 x float>* %a, <4 x float>* %b, <4 x float>* %c, <4 x float>* %d) {
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%al = load <4 x float>, <4 x float>* %a
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%bl = load <4 x float>, <4 x float>* %b
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%cl = load <4 x float>, <4 x float>* %c
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%dl = load <4 x float>, <4 x float>* %d
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%ar = fadd <4 x float> %al, %bl
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%br = fadd <4 x float> %bl, %cl
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%cr = fadd <4 x float> %cl, %dl
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%dr = fadd <4 x float> %dl, %al
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; The sizes below are conservative. AArch64TargetLowering
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; conservatively assumes the entire vector is stored.
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tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)
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; CHECK: ST2i32 {{.*}} :: (store 32 {{.*}})
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tail call void @llvm.aarch64.neon.st3lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, i64 1, float* %res)
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; CHECK: ST3i32 {{.*}} :: (store 48 {{.*}})
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tail call void @llvm.aarch64.neon.st4lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, <4 x float> %cr, <4 x float> %dr, i64 1, float* %res)
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; CHECK: ST4i32 {{.*}} :: (store 64 {{.*}})
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ret void
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}
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