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Sam Parker
3757f28f1d
Recommitting r329283, third time lucky... If the SRL node is only used by an AND, we may be able to set the ExtVT to the width of the mask, making the AND redundant. To support this, another check has been added in isLegalNarrowLoad which queries whether the load is valid. Differential Revision: https://reviews.llvm.org/D41350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329551 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
595 B
LLVM
19 lines
595 B
LLVM
; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
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; CHECK-LABEL: trunc_srl_load
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; CHECK-NOT: lhz 4, 4(0)
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; CHECK: lhz 4, 2(0)
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define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
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entry:
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%bf.load.i = load i64, i64* null, align 8
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%bf.lshr.i = lshr i64 %bf.load.i, 32
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%0 = trunc i64 %bf.lshr.i to i32
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%bf.cast.i = and i32 %0, 65535
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%cmp.i = icmp ugt i32 %bf.cast.i, %AttrArgNo
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br i1 %cmp.i, label %exit, label %cond.false
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exit: ; preds = %entry
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unreachable
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cond.false: ; preds = %entry
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unreachable
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}
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