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12df467aac
If the arch is P8, we will select XFLOAD to load the floating point, and then, expand it to vsx and non-vsx X-form instruction post RA. This patch is trying to convert the X-form to D-form if it meets the requirement that one operand of the x-form inst is the special Zero register, and another operand fed by add inst. i.e. y = add imm, reg LFDX. 0, y --> LFD imm(reg) Reviewers: Nemanjai Differential Revision: https://reviews.llvm.org/D49007 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@340149 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
2.3 KiB
LLVM
57 lines
2.3 KiB
LLVM
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
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; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
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; Function Attrs: nounwind
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define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
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; CHECK-LABEL: @testBranchCoal
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; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0
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; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]]
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; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
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; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha
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; CHECK-DAG: xxlxor 2, 2, 2
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; CHECK-NOT: beq
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; CHECK-DAG: lfd 1, .LCPI0_0@toc@l([[LD1REG]])
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; CHECK-DAG: lfd 3, .LCPI0_1@toc@l([[LD2REG]])
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; CHECK: .LBB[[LAB1]]
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; CHECK: xsadddp 0, 1, 2
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; CHECK: xsadddp 1, 0, 3
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; CHECK: blr
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; CHECK-NOCOALESCE-LABEL: testBranchCoal:
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; CHECK-NOCOALESCE: # %bb.0: # %entry
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; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0
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; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5
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; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry
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; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6
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; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry
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; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4
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; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry
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; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; CHECK-NOCOALESCE-NEXT: lfd 3, .LCPI0_1@toc@l(3)
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; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry
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; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2
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; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3
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; CHECK-NOCOALESCE-NEXT: blr
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; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry
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; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
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; CHECK-NOCOALESCE-NEXT: lfd 1, .LCPI0_0@toc@l(3)
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; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2
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; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry
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; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2
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; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_3
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; CHECK-NOCOALESCE-NEXT: b .LBB0_4
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entry:
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%test = icmp eq i32 %x, 0
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%tmp1 = select i1 %test, double %a, double 2.000000e-03
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%tmp2 = select i1 %test, double %b, double 0.000000e+00
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%tmp3 = select i1 %test, double %c, double 5.000000e-03
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%res1 = fadd double %tmp1, %tmp2
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%result = fadd double %res1, %tmp3
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ret double %result
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}
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