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The pass to expand ISEL instructions into if-then-else sequences in patch D23630 is currently disabled. This patch partially enable it by always removing the unnecessary ISELs (all registers used by the ISELs are the same one) and folding the ISELs which have the same input registers into unconditional copies. Differential Revision: https://reviews.llvm.org/D40497 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320414 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
3.3 KiB
LLVM
72 lines
3.3 KiB
LLVM
target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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; This file mainly tests the case that the two input registers of the ISEL instruction are the same register.
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; The foldable ISEL in this test case is introduced at simple register coalescing stage.
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; Before that stage we have:
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; %vreg18<def> = ISEL8 %vreg5, %vreg2, %vreg15<undef>;
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; At simple register coalescing stage, the register coalescer figures out it could remove the copy
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; from %vreg2 to %vreg5, put the original value %X3 into %vreg5 directly
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; erased: 336r %vreg5<def> = COPY %vreg2
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; updated: 288B %vreg5<def> = COPY %X3;
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; After that we have:
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; updated: 416B %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>;
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; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE
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; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
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%"struct.pov::ot_block_struct" = type { %"struct.pov::ot_block_struct"*, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 }
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%"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", %"struct.pov::ot_block_struct"*, [8 x %"struct.pov::ot_node_struct"*] }
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%"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 }
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define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(%"struct.pov::ot_block_struct"* %new_block) {
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; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE:
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; Note: the following line fold the original isel (isel r4, r3, r3)
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; CHECK-GEN-ISEL-TRUE: mr r4, r3
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; CHECK-GEN-ISEL-TRUE: isel r29, r5, r6, 4*cr5+lt
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; CHECK-GEN-ISEL-TRUE: blr
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;
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; CHECK-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE:
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; CHECK: mr r4, r3
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; CHECK: bc 12, 4*cr5+lt, .LBB0_3
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; CHECK: # %bb.2:
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; CHECK: ori r29, r6, 0
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; CHECK: b .LBB0_4
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; CHECK: .LBB0_3:
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; CHECK: addi r29, r5, 0
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; CHECK: .LBB0_4:
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; CHECK: blr
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entry:
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br label %while.cond11
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while.cond11:
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%this_node.0250 = phi %"struct.pov::ot_node_struct"* [ undef, %entry ], [ %1, %cond.false21.i156 ], [ %1, %cond.true18.i153 ]
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%temp_id.sroa.21.1 = phi i32 [ undef, %entry ], [ %shr2039.i152, %cond.true18.i153 ], [ %div24.i155, %cond.false21.i156 ]
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%0 = load i32, i32* undef, align 4
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%cmp17 = icmp eq i32 0, %0
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br i1 %cmp17, label %lor.rhs, label %while.body21
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lor.rhs:
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%Values = getelementptr inbounds %"struct.pov::ot_node_struct", %"struct.pov::ot_node_struct"* %this_node.0250, i64 0, i32 1
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store %"struct.pov::ot_block_struct"* %new_block, %"struct.pov::ot_block_struct"** %Values, align 8
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ret void
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while.body21:
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%call.i84 = tail call i8* @ZN3pov10pov_callocEmmPKciS1_pov()
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store i8* %call.i84, i8** undef, align 8
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%1 = bitcast i8* %call.i84 to %"struct.pov::ot_node_struct"*
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br i1 undef, label %cond.true18.i153, label %cond.false21.i156
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cond.true18.i153:
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%shr2039.i152 = lshr i32 %temp_id.sroa.21.1, 1
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br label %while.cond11
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cond.false21.i156:
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%add23.i154 = add nsw i32 %temp_id.sroa.21.1, 1
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%div24.i155 = sdiv i32 %add23.i154, 2
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br label %while.cond11
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}
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declare i8* @ZN3pov10pov_callocEmmPKciS1_pov()
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