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c486a43e86
Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337347 91177308-0d34-0410-b5e6-96231b3b80d8
220 lines
4.6 KiB
LLVM
220 lines
4.6 KiB
LLVM
; FIXME: FastISel currently returns false if it hits code that uses VSX
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; registers and with -fast-isel-abort=1 turned on the test case will then fail.
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; When fastisel better supports VSX fix up this test case.
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;
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; RUN: llc -relocation-model=static < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
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; RUN: llc -relocation-model=static < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=spe -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 | FileCheck %s --check-prefix=SPE
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; This test verifies that load/store instructions are properly generated,
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; and that they pass MI verification.
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@a = global i8 1, align 1
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@b = global i16 2, align 2
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@c = global i32 4, align 4
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@d = global i64 8, align 8
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@e = global float 1.25, align 4
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@f = global double 3.5, align 8
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%struct.s = type<{ i8, i32 }>
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%struct.t = type<{ i8, i64 }>
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@g = global %struct.s <{ i8 1, i32 2 }>, align 1
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@h = global %struct.t <{ i8 1, i64 2 }>, align 1
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@i = common global [8192 x i64] zeroinitializer, align 8
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; load
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define i8 @t1() nounwind {
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; ELF64: t1
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%1 = load i8, i8* @a, align 1
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; ELF64: lbz
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%2 = add nsw i8 %1, 1
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; ELF64: addi
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ret i8 %2
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}
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define i16 @t2() nounwind {
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; ELF64: t2
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%1 = load i16, i16* @b, align 2
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; ELF64: lhz
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%2 = add nsw i16 %1, 1
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; ELF64: addi
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ret i16 %2
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}
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define i32 @t3() nounwind {
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; ELF64: t3
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%1 = load i32, i32* @c, align 4
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; ELF64: lwz
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%2 = add nsw i32 %1, 1
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; ELF64: addi
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ret i32 %2
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}
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define i64 @t4() nounwind {
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; ELF64: t4
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%1 = load i64, i64* @d, align 4
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; ELF64: ld
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%2 = add nsw i64 %1, 1
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; ELF64: addi
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ret i64 %2
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}
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define float @t5() nounwind {
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; ELF64: t5
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; SPE: t5
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%1 = load float, float* @e, align 4
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; ELF64: lfs
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; SPE: lwz
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%2 = fadd float %1, 1.0
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; ELF64: fadds
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; SPE: efsadd
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ret float %2
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}
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define double @t6() nounwind {
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; ELF64: t6
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; SPE: t6
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%1 = load double, double* @f, align 8
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; ELF64: lfd
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; SPE: evldd
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%2 = fadd double %1, 1.0
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; ELF64: fadd
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; SPE: efdadd
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ret double %2
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}
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; store
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define void @t7(i8 %v) nounwind {
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; ELF64: t7
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%1 = add nsw i8 %v, 1
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store i8 %1, i8* @a, align 1
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; ELF64: addis
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; ELF64: addi
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; ELF64: addi
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; ELF64: stb
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ret void
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}
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define void @t8(i16 %v) nounwind {
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; ELF64: t8
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%1 = add nsw i16 %v, 1
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store i16 %1, i16* @b, align 2
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; ELF64: addis
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; ELF64: addi
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; ELF64: addi
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; ELF64: sth
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ret void
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}
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define void @t9(i32 %v) nounwind {
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; ELF64: t9
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%1 = add nsw i32 %v, 1
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store i32 %1, i32* @c, align 4
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; ELF64: addis
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; ELF64: addi
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; ELF64: addi
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; ELF64: stw
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ret void
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}
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define void @t10(i64 %v) nounwind {
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; ELF64: t10
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%1 = add nsw i64 %v, 1
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store i64 %1, i64* @d, align 4
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; ELF64: addis
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; ELF64: addi
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; ELF64: addi
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; ELF64: std
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ret void
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}
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define void @t11(float %v) nounwind {
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; ELF64: t11
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; SPE: t11
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%1 = fadd float %v, 1.0
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store float %1, float* @e, align 4
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; ELF64: fadds
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; ELF64: stfs
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; SPE: efsadd
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; SPE: stw
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ret void
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}
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define void @t12(double %v) nounwind {
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; ELF64: t12
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; SPE: t12
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%1 = fadd double %v, 1.0
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store double %1, double* @f, align 8
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; ELF64: fadd
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; ELF64: stfd
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; SPE: efdadd
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; SPE: evstdd
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ret void
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}
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;; lwa requires an offset divisible by 4, so we need lwax here.
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define i64 @t13() nounwind {
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; ELF64: t13
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%1 = load i32, i32* getelementptr inbounds (%struct.s, %struct.s* @g, i32 0, i32 1), align 1
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%2 = sext i32 %1 to i64
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; ELF64: li
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; ELF64: lwax
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%3 = add nsw i64 %2, 1
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; ELF64: addi
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ret i64 %3
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}
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;; ld requires an offset divisible by 4, so we need ldx here.
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define i64 @t14() nounwind {
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; ELF64: t14
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%1 = load i64, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
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; ELF64: li
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; ELF64: ldx
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%2 = add nsw i64 %1, 1
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; ELF64: addi
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ret i64 %2
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}
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;; std requires an offset divisible by 4, so we need stdx here.
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define void @t15(i64 %v) nounwind {
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; ELF64: t15
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%1 = add nsw i64 %v, 1
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store i64 %1, i64* getelementptr inbounds (%struct.t, %struct.t* @h, i32 0, i32 1), align 1
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; ELF64: addis
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; ELF64: addi
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; ELF64: addi
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; ELF64: li
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; ELF64: stdx
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ret void
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}
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;; ld requires an offset that fits in 16 bits, so we need ldx here.
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define i64 @t16() nounwind {
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; ELF64: t16
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%1 = load i64, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
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; ELF64: lis
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; ELF64: ori
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; ELF64: ldx
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%2 = add nsw i64 %1, 1
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; ELF64: addi
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ret i64 %2
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}
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;; std requires an offset that fits in 16 bits, so we need stdx here.
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define void @t17(i64 %v) nounwind {
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; ELF64: t17
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%1 = add nsw i64 %v, 1
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store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
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; ELF64: addis
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; ELF64: addi
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; ELF64: addi
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; ELF64: lis
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; ELF64: ori
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; ELF64: stdx
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ret void
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}
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