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1f9881f51a
Current implementation always allocates the parameter save area conservatively for fastcc functions. There is no reason to allocate the parameter save area if all the parameters can be passed via registers. Differential Revision: https://reviews.llvm.org/D42602 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@325581 91177308-0d34-0410-b5e6-96231b3b80d8
142 lines
5.0 KiB
LLVM
142 lines
5.0 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
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; Paramater Save Area is not needed if number of parameter does not exceed
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; number of registers
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; ------------------------------------------------------------------------------
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; Max number of GPR is 8
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define linkonce_odr void
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@WithoutParamArea(i8* %a, i32 signext %b) align 2 {
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entry:
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call fastcc void @fastccFunc(i32 signext 1)
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ret void
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; CHECK-LABEL: WithoutParamArea
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; CHECK: stdu 1, -32(1)
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; CHECK: blr
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}
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declare fastcc void @fastccFunc(i32 signext %level) unnamed_addr
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; No need for Parameter Save Area if only 8 GPRs is needed.
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define linkonce_odr void @WithoutParamArea2(i8* %a, i32 signext %b) align 2 {
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entry:
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call fastcc void @eightArgs(i32 signext 1, i32 signext 2, i32 signext 3,
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i32 signext 4, i32 signext 5, i32 signext 6,
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i32 signext 7, i32 signext 8)
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ret void
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; CHECK-LABEL: WithoutParamArea2
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; CHECK: stdu 1, -32(1)
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; CHECK: blr
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}
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declare fastcc void
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@eightArgs(i32 signext %level, i32 signext %level2, i32 signext %level3,
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i32 signext %level4, i32 signext %level5, i32 signext %level6,
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i32 signext %level7, i32 signext %level8) unnamed_addr
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; No need for Parameter Save Area for calls that utiliizes 8 GPR and 2 FPR.
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define linkonce_odr void @WithoutParamArea3(i8* %a, i32 signext %b) align 2 {
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entry:
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call fastcc void
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@mixedArgs(i32 signext 1, float 1.0, i32 signext 2, float 2.0,
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i32 signext 3, i32 signext 4, i32 signext 5, i32 signext 6,
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i32 signext 7, i32 signext 8) ret void
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ret void
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; CHECK-LABEL : WithoutParamArea3
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; CHECK: stdu 1, -32(1)
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; CHECK: blr
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}
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declare fastcc void
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@mixedArgs(i32 signext %level, float %levelf1, i32 signext %level2,
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float %levelf2, i32 signext %level3, i32 signext %level4,
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i32 signext %level5, i32 signext %level6, i32 signext %level7,
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i32 signext %level8) unnamed_addr
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; Pass by value usage requiring less GPR then available
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%"myClass::Mem" = type { i8, i8, i16, i32, i32, i32, i64 }
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define internal fastcc void @CallPassByValue(%"myClass::Mem"* %E) align 2 {
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entry:
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call fastcc void @PassByValue(%"myClass::Mem"* byval nonnull align 8 undef);
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ret void
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; CHECK-LABEL : PassByValue
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; CHECK: stdu 1, -32(1)
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; CHECK: blr
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}
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declare dso_local fastcc void
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@PassByValue(%"myClass::Mem"* byval nocapture readonly align 8) align 2
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; Verify Paramater Save Area is allocated if parameter exceed the number that
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; can be passed via registers
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; ------------------------------------------------------------------------------
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; Max number of GPR is 8
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define linkonce_odr void @WithParamArea(i8 * %a, i32 signext %b) align 2 {
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entry:
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call fastcc void @nineArgs(i32 signext 1, i32 signext 2, i32 signext 3,
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i32 signext 4, i32 signext 5, i32 signext 6,
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i32 signext 7, i32 signext 8, i32 signext 9)
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ret void
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; CHECK-LABEL: WithParamArea
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; CHECK: stdu 1, -96(1)
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; CHECK: blr
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}
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declare fastcc void @nineArgs(i32 signext %level, i32 signext %level2,
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i32 signext %level3, i32 signext %level4, i32 signext %level5,
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i32 signext %level6, i32 signext %level7, i32 signext %level8,
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i32 signext %level9) unnamed_addr
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; Max number of FPR for parameter passing is 13
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define linkonce_odr void @WithParamArea2(i8* %a, i32 signext %b) align 2 {
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entry:
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call fastcc void @funcW14FloatArgs(float 1.0, float 2.0, float 3.0,
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float 4.0, float 5.0, float 6.0, float 7.0, float 8.0, float 1.0,
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float 2.0, float 3.0, float 4.0, float 5.0, float 14.0)
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ret void
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; CHECK-LABEL: WithParamArea2
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; CHECK: stdu 1, -96(1)
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; CHECK: blr
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}
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declare fastcc void
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@funcW14FloatArgs(float %level, float %level2, float %level3,
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float %level4, float %level5, float %level6,
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float %level7, float %level8, float %level9,
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float %level10, float %level11, float %level12,
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float %level13, float %level14);
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; Pass by value usage requires more GPR then available
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%"myClass::MemA" = type { i8, i8, i16, i32, i32, i32, i64 }
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%"myClass::MemB" = type { i32*, i32, i32, %"myClass::MemB"** }
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%"myClass::MemC" = type { %"myClass::MemD"*, %"myClass::MemC"*, i64 }
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%"myClass::MemD" = type { %"myClass::MemB"*, %"myClass::MemC"*, i8, i8, i16,
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i32 }
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%"myStruct::MemF" = type { i32, %"myClass::MemA"*, %"myClass::MemA"*, i64, i64 }
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%"myClass::MemK" = type { i32, %"myClass::MemD"*, %"myClass::MemD"*, i64, i32,
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i64, i8, i32, %"myStruct::MemF",
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i8, %"myClass::MemA"* }
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define internal fastcc void @AggMemExprEmitter(%"myClass::MemK"* %E) align 2 {
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entry:
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call fastcc void @MemExprEmitterInitialization(%"myClass::MemK" *
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byval nonnull align 8 undef);
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ret void
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; CHECK-LABEL : AggMemExprEmitter
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; CHECK: stdu 1, -144(1)
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; CHECK: blr
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}
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declare dso_local fastcc void
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@MemExprEmitterInitialization(%"myClass::MemK" *
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byval nocapture readonly align 8) align 2
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