mirror of
https://github.com/RPCS3/llvm.git
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c486a43e86
Summary: The Signal Processing Engine (SPE) is found on NXP/Freescale e500v1, e500v2, and several e200 cores. This adds support targeting the e500v2, as this is more common than the e500v1, and is in SoCs still on the market. This patch is very intrusive because the SPE is binary incompatible with the traditional FPU. After discussing with others, the cleanest solution was to make both SPE and FPU features on top of a base PowerPC subset, so all FPU instructions are now wrapped with HasFPU predicates. Supported by this are: * Code generation following the SPE ABI at the LLVM IR level (calling conventions) * Single- and Double-precision math at the level supported by the APU. Still to do: * Vector operations * SPE intrinsics As this changes the Callee-saved register list order, one test, which tests the precise generated code, was updated to account for the new register order. Reviewed by: nemanjai Differential Revision: https://reviews.llvm.org/D44830 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337347 91177308-0d34-0410-b5e6-96231b3b80d8
543 lines
10 KiB
LLVM
543 lines
10 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
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; RUN: -mattr=+spe | FileCheck %s
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declare float @llvm.fabs.float(float)
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define float @test_float_abs(float %a) #0 {
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entry:
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%0 = tail call float @llvm.fabs.float(float %a)
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ret float %0
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; CHECK-LABEL: test_float_abs
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; CHECK: efsabs 3, 3
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; CHECK: blr
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}
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define float @test_fnabs(float %a) #0 {
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entry:
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%0 = tail call float @llvm.fabs.float(float %a)
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%sub = fsub float -0.000000e+00, %0
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ret float %sub
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; CHECK-LABEL: @test_fnabs
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; CHECK: efsnabs
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; CHECK: blr
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}
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define float @test_fdiv(float %a, float %b) {
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entry:
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%v = fdiv float %a, %b
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ret float %v
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; CHECK-LABEL: test_fdiv
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; CHECK: efsdiv
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; CHECK: blr
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}
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define float @test_fmul(float %a, float %b) {
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entry:
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%v = fmul float %a, %b
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ret float %v
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; CHECK-LABEL @test_fmul
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; CHECK: efsmul
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; CHECK: blr
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}
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define float @test_fadd(float %a, float %b) {
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entry:
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%v = fadd float %a, %b
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ret float %v
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; CHECK-LABEL @test_fadd
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; CHECK: efsadd
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; CHECK: blr
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}
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define float @test_fsub(float %a, float %b) {
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entry:
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%v = fsub float %a, %b
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ret float %v
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; CHECK-LABEL @test_fsub
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; CHECK: efssub
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; CHECK: blr
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}
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define float @test_fneg(float %a) {
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entry:
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%v = fsub float -0.0, %a
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ret float %v
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; CHECK-LABEL @test_fneg
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; CHECK: efsneg
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; CHECK: blr
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}
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define float @test_dtos(double %a) {
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entry:
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%v = fptrunc double %a to float
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ret float %v
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; CHECK-LABEL: test_dtos
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; CHECK: efscfd
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; CHECK: blr
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}
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define i1 @test_fcmpgt(float %a, float %b) {
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entry:
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%r = fcmp ogt float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpgt
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; CHECK: efscmpgt
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; CHECK: blr
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}
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define i1 @test_fcmpugt(float %a, float %b) {
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entry:
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%r = fcmp ugt float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpugt
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; CHECK: efscmpgt
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; CHECK: blr
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}
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define i1 @test_fcmple(float %a, float %b) {
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entry:
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%r = fcmp ole float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmple
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; CHECK: efscmpgt
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; CHECK: blr
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}
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define i1 @test_fcmpule(float %a, float %b) {
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entry:
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%r = fcmp ule float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpule
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; CHECK: efscmpgt
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; CHECK: blr
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}
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define i1 @test_fcmpeq(float %a, float %b) {
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entry:
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%r = fcmp oeq float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpeq
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; CHECK: efscmpeq
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; CHECK: blr
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}
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; (un)ordered tests are expanded to une and oeq so verify
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define i1 @test_fcmpuno(float %a, float %b) {
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entry:
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%r = fcmp uno float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpuno
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; CHECK: efscmpeq
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; CHECK: efscmpeq
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; CHECK: crand
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; CHECK: blr
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}
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define i1 @test_fcmpord(float %a, float %b) {
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entry:
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%r = fcmp ord float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpord
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; CHECK: efscmpeq
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; CHECK: efscmpeq
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; CHECK: crnand
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; CHECK: blr
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}
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define i1 @test_fcmpueq(float %a, float %b) {
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entry:
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%r = fcmp ueq float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpueq
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; CHECK: efscmpeq
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; CHECK: blr
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}
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define i1 @test_fcmpne(float %a, float %b) {
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entry:
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%r = fcmp one float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpne
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; CHECK: efscmpeq
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; CHECK: blr
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}
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define i1 @test_fcmpune(float %a, float %b) {
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entry:
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%r = fcmp une float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpune
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; CHECK: efscmpeq
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; CHECK: blr
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}
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define i1 @test_fcmplt(float %a, float %b) {
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entry:
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%r = fcmp olt float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmplt
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; CHECK: efscmplt
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; CHECK: blr
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}
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define i1 @test_fcmpult(float %a, float %b) {
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entry:
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%r = fcmp ult float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpult
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; CHECK: efscmplt
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; CHECK: blr
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}
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define i1 @test_fcmpge(float %a, float %b) {
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entry:
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%r = fcmp oge float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpge
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; CHECK: efscmplt
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; CHECK: blr
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}
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define i1 @test_fcmpuge(float %a, float %b) {
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entry:
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%r = fcmp uge float %a, %b
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ret i1 %r
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; CHECK-LABEL: test_fcmpuge
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; CHECK: efscmplt
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; CHECK: blr
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}
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define i32 @test_ftoui(float %a) {
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%v = fptoui float %a to i32
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ret i32 %v
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; CHECK-LABEL: test_ftoui
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; CHECK: efsctuiz
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}
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define i32 @test_ftosi(float %a) {
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%v = fptosi float %a to i32
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ret i32 %v
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; CHECK-LABEL: test_ftosi
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; CHECK: efsctsiz
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}
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define float @test_ffromui(i32 %a) {
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%v = uitofp i32 %a to float
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ret float %v
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; CHECK-LABEL: test_ffromui
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; CHECK: efscfui
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}
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define float @test_ffromsi(i32 %a) {
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%v = sitofp i32 %a to float
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ret float %v
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; CHECK-LABEL: test_ffromsi
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; CHECK: efscfsi
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}
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define i32 @test_fasmconst(float %x) {
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entry:
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%x.addr = alloca float, align 8
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store float %x, float* %x.addr, align 8
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%0 = load float, float* %x.addr, align 8
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%1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0)
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ret i32 %1
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; CHECK-LABEL: test_fasmconst
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; Check that it's not loading a double
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; CHECK-NOT: evldd
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; CHECK: #APP
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; CHECK: efsctsi
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; CHECK: #NO_APP
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}
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; Double tests
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define void @test_double_abs(double * %aa) #0 {
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entry:
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%0 = load double, double * %aa
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%1 = tail call double @llvm.fabs.f64(double %0) #2
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store double %1, double * %aa
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ret void
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; CHECK-LABEL: test_double_abs
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; CHECK: efdabs
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; CHECK: blr
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}
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; Function Attrs: nounwind readnone
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declare double @llvm.fabs.f64(double) #1
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define void @test_dnabs(double * %aa) #0 {
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entry:
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%0 = load double, double * %aa
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%1 = tail call double @llvm.fabs.f64(double %0) #2
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%sub = fsub double -0.000000e+00, %1
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store double %sub, double * %aa
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ret void
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}
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; CHECK-LABEL: @test_dnabs
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; CHECK: efdnabs
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; CHECK: blr
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define double @test_ddiv(double %a, double %b) {
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entry:
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%v = fdiv double %a, %b
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ret double %v
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; CHECK-LABEL: test_ddiv
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; CHECK: efddiv
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; CHECK: blr
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}
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define double @test_dmul(double %a, double %b) {
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entry:
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%v = fmul double %a, %b
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ret double %v
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; CHECK-LABEL @test_dmul
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; CHECK: efdmul
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; CHECK: blr
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}
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define double @test_dadd(double %a, double %b) {
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entry:
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%v = fadd double %a, %b
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ret double %v
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; CHECK-LABEL @test_dadd
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; CHECK: efdadd
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; CHECK: blr
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}
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define double @test_dsub(double %a, double %b) {
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entry:
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%v = fsub double %a, %b
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ret double %v
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; CHECK-LABEL @test_dsub
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; CHECK: efdsub
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; CHECK: blr
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}
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define double @test_dneg(double %a) {
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entry:
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%v = fsub double -0.0, %a
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ret double %v
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; CHECK-LABEL @test_dneg
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; CHECK: blr
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}
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define double @test_stod(float %a) {
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entry:
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%v = fpext float %a to double
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ret double %v
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; CHECK-LABEL: test_stod
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; CHECK: efdcfs
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; CHECK: blr
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}
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; (un)ordered tests are expanded to une and oeq so verify
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define i1 @test_dcmpuno(double %a, double %b) {
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entry:
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%r = fcmp uno double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpuno
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; CHECK: efdcmpeq
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; CHECK: efdcmpeq
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; CHECK: crand
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; CHECK: blr
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}
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define i1 @test_dcmpord(double %a, double %b) {
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entry:
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%r = fcmp ord double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpord
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; CHECK: efdcmpeq
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; CHECK: efdcmpeq
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; CHECK: crnand
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; CHECK: blr
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}
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define i1 @test_dcmpgt(double %a, double %b) {
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entry:
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%r = fcmp ogt double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpgt
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; CHECK: efdcmpgt
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; CHECK: blr
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}
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define i1 @test_dcmpugt(double %a, double %b) {
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entry:
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%r = fcmp ugt double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpugt
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; CHECK: efdcmpgt
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; CHECK: blr
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}
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define i1 @test_dcmple(double %a, double %b) {
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entry:
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%r = fcmp ole double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmple
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; CHECK: efdcmpgt
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; CHECK: blr
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}
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define i1 @test_dcmpule(double %a, double %b) {
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entry:
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%r = fcmp ule double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpule
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; CHECK: efdcmpgt
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; CHECK: blr
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}
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define i1 @test_dcmpeq(double %a, double %b) {
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entry:
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%r = fcmp oeq double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpeq
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; CHECK: efdcmpeq
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; CHECK: blr
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}
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define i1 @test_dcmpueq(double %a, double %b) {
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entry:
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%r = fcmp ueq double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpueq
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; CHECK: efdcmpeq
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; CHECK: blr
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}
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define i1 @test_dcmpne(double %a, double %b) {
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entry:
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%r = fcmp one double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpne
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; CHECK: efdcmpeq
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; CHECK: blr
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}
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define i1 @test_dcmpune(double %a, double %b) {
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entry:
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%r = fcmp une double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpune
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; CHECK: efdcmpeq
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; CHECK: blr
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}
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define i1 @test_dcmplt(double %a, double %b) {
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entry:
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%r = fcmp olt double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmplt
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; CHECK: efdcmplt
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; CHECK: blr
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}
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define i1 @test_dcmpult(double %a, double %b) {
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entry:
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%r = fcmp ult double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpult
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; CHECK: efdcmplt
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; CHECK: blr
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}
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define i1 @test_dcmpge(double %a, double %b) {
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entry:
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%r = fcmp oge double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpge
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; CHECK: efdcmplt
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; CHECK: blr
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}
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define i1 @test_dcmpuge(double %a, double %b) {
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entry:
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%r = fcmp uge double %a, %b
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ret i1 %r
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; CHECK-LABEL: test_dcmpuge
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; CHECK: efdcmplt
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; CHECK: blr
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}
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define double @test_dselect(double %a, double %b, i1 %c) {
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entry:
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%r = select i1 %c, double %a, double %b
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ret double %r
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; CHECK-LABEL: test_dselect
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; CHECK: andi.
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; CHECK: bc
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; CHECK: evldd
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; CHECK: b
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; CHECK: evldd
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; CHECK: evstdd
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; CHECK: blr
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}
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define i32 @test_dtoui(double %a) {
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entry:
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%v = fptoui double %a to i32
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ret i32 %v
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; CHECK-LABEL: test_dtoui
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; CHECK: efdctuiz
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}
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define i32 @test_dtosi(double %a) {
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entry:
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%v = fptosi double %a to i32
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ret i32 %v
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; CHECK-LABEL: test_dtosi
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; CHECK: efdctsiz
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}
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define double @test_dfromui(i32 %a) {
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entry:
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%v = uitofp i32 %a to double
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ret double %v
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; CHECK-LABEL: test_dfromui
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; CHECK: efdcfui
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}
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define double @test_dfromsi(i32 %a) {
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entry:
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%v = sitofp i32 %a to double
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ret double %v
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; CHECK-LABEL: test_dfromsi
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; CHECK: efdcfsi
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}
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define i32 @test_dasmconst(double %x) {
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entry:
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%x.addr = alloca double, align 8
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store double %x, double* %x.addr, align 8
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%0 = load double, double* %x.addr, align 8
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%1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0)
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ret i32 %1
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; CHECK-LABEL: test_dasmconst
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; CHECK: evldd
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; CHECK: #APP
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; CHECK: efdctsi
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; CHECK: #NO_APP
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}
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define double @test_spill(double %a) nounwind {
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entry:
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%0 = fadd double %a, %a
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call void asm sideeffect "","~{r0},~{r3},~{s4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind
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%1 = fadd double %0, 3.14159
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br label %return
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return:
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|
ret double %1
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; CHECK-LABEL: test_spill
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|
; CHECK: efdadd
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; CHECK: evstdd
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|
; CHECK: evldd
|
|
}
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