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0819555500
The indexed variant of vfmal.f16 and vfmsl.f16 instructions use the uppser bits of the indexed operand to store the index (1 bit for the double variant, 2 bits for the quad). This limits the usable registers to d0 - d7 or s0 - s15. This patch enforces this limitation. Differential Revision: https://reviews.llvm.org/D59021 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355707 91177308-0d34-0410-b5e6-96231b3b80d8