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730 lines
22 KiB
C++
730 lines
22 KiB
C++
//===---- AVRAsmParser.cpp - Parse AVR assembly to MCInst instructions ----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AVR.h"
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#include "AVRRegisterInfo.h"
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#include "MCTargetDesc/AVRMCELFStreamer.h"
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#include "MCTargetDesc/AVRMCExpr.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCParser/MCTargetAsmParser.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/TargetRegistry.h"
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#include <sstream>
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#define DEBUG_TYPE "avr-asm-parser"
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using namespace llvm;
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namespace {
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/// Parses AVR assembly from a stream.
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class AVRAsmParser : public MCTargetAsmParser {
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const MCSubtargetInfo &STI;
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MCAsmParser &Parser;
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const MCRegisterInfo *MRI;
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const std::string GENERATE_STUBS = "gs";
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#define GET_ASSEMBLER_HEADER
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#include "AVRGenAsmMatcher.inc"
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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bool MatchingInlineAsm) override;
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
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bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) override;
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bool ParseDirective(AsmToken DirectiveID) override;
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OperandMatchResultTy parseMemriOperand(OperandVector &Operands);
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bool parseOperand(OperandVector &Operands);
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int parseRegisterName(unsigned (*matchFn)(StringRef));
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int parseRegisterName();
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int parseRegister();
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bool tryParseRegisterOperand(OperandVector &Operands);
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bool tryParseExpression(OperandVector &Operands);
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bool tryParseRelocExpression(OperandVector &Operands);
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void eatComma();
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unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
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unsigned Kind) override;
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unsigned toDREG(unsigned Reg, unsigned From = AVR::sub_lo) {
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MCRegisterClass const *Class = &AVRMCRegisterClasses[AVR::DREGSRegClassID];
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return MRI->getMatchingSuperReg(Reg, From, Class);
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}
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bool emit(MCInst &Instruction, SMLoc const &Loc, MCStreamer &Out) const;
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bool invalidOperand(SMLoc const &Loc, OperandVector const &Operands,
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uint64_t const &ErrorInfo);
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bool missingFeature(SMLoc const &Loc, uint64_t const &ErrorInfo);
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bool parseLiteralValues(unsigned SizeInBytes, SMLoc L);
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public:
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AVRAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
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const MCInstrInfo &MII, const MCTargetOptions &Options)
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: MCTargetAsmParser(Options, STI, MII), STI(STI), Parser(Parser) {
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MCAsmParserExtension::Initialize(Parser);
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MRI = getContext().getRegisterInfo();
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setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
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}
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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};
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/// An parsed AVR assembly operand.
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class AVROperand : public MCParsedAsmOperand {
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typedef MCParsedAsmOperand Base;
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enum KindTy { k_Immediate, k_Register, k_Token, k_Memri } Kind;
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public:
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AVROperand(StringRef Tok, SMLoc const &S)
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: Base(), Kind(k_Token), Tok(Tok), Start(S), End(S) {}
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AVROperand(unsigned Reg, SMLoc const &S, SMLoc const &E)
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: Base(), Kind(k_Register), RegImm({Reg, nullptr}), Start(S), End(E) {}
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AVROperand(MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
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: Base(), Kind(k_Immediate), RegImm({0, Imm}), Start(S), End(E) {}
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AVROperand(unsigned Reg, MCExpr const *Imm, SMLoc const &S, SMLoc const &E)
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: Base(), Kind(k_Memri), RegImm({Reg, Imm}), Start(S), End(E) {}
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struct RegisterImmediate {
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unsigned Reg;
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MCExpr const *Imm;
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};
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union {
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StringRef Tok;
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RegisterImmediate RegImm;
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};
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SMLoc Start, End;
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public:
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(Kind == k_Register && "Unexpected operand kind");
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(getReg()));
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}
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void addExpr(MCInst &Inst, const MCExpr *Expr) const {
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// Add as immediate when possible
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if (!Expr)
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Inst.addOperand(MCOperand::createImm(0));
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else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
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Inst.addOperand(MCOperand::createImm(CE->getValue()));
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else
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Inst.addOperand(MCOperand::createExpr(Expr));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(Kind == k_Immediate && "Unexpected operand kind");
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assert(N == 1 && "Invalid number of operands!");
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const MCExpr *Expr = getImm();
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addExpr(Inst, Expr);
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}
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/// Adds the contained reg+imm operand to an instruction.
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void addMemriOperands(MCInst &Inst, unsigned N) const {
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assert(Kind == k_Memri && "Unexpected operand kind");
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assert(N == 2 && "Invalid number of operands");
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Inst.addOperand(MCOperand::createReg(getReg()));
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addExpr(Inst, getImm());
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}
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void addImmCom8Operands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// The operand is actually a imm8, but we have its bitwise
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// negation in the assembly source, so twiddle it here.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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Inst.addOperand(MCOperand::createImm(~(uint8_t)CE->getValue()));
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}
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bool isImmCom8() const {
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if (!isImm()) return false;
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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int64_t Value = CE->getValue();
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return isUInt<8>(Value);
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}
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bool isReg() const { return Kind == k_Register; }
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bool isImm() const { return Kind == k_Immediate; }
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bool isToken() const { return Kind == k_Token; }
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bool isMem() const { return Kind == k_Memri; }
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bool isMemri() const { return Kind == k_Memri; }
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StringRef getToken() const {
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assert(Kind == k_Token && "Invalid access!");
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return Tok;
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}
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unsigned getReg() const {
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assert((Kind == k_Register || Kind == k_Memri) && "Invalid access!");
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return RegImm.Reg;
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}
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const MCExpr *getImm() const {
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assert((Kind == k_Immediate || Kind == k_Memri) && "Invalid access!");
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return RegImm.Imm;
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}
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static std::unique_ptr<AVROperand> CreateToken(StringRef Str, SMLoc S) {
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return make_unique<AVROperand>(Str, S);
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}
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static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S,
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SMLoc E) {
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return make_unique<AVROperand>(RegNum, S, E);
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}
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static std::unique_ptr<AVROperand> CreateImm(const MCExpr *Val, SMLoc S,
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SMLoc E) {
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return make_unique<AVROperand>(Val, S, E);
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}
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static std::unique_ptr<AVROperand>
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CreateMemri(unsigned RegNum, const MCExpr *Val, SMLoc S, SMLoc E) {
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return make_unique<AVROperand>(RegNum, Val, S, E);
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}
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void makeToken(StringRef Token) {
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Kind = k_Token;
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Tok = Token;
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}
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void makeReg(unsigned RegNo) {
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Kind = k_Register;
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RegImm = {RegNo, nullptr};
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}
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void makeImm(MCExpr const *Ex) {
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Kind = k_Immediate;
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RegImm = {0, Ex};
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}
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void makeMemri(unsigned RegNo, MCExpr const *Imm) {
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Kind = k_Memri;
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RegImm = {RegNo, Imm};
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}
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SMLoc getStartLoc() const { return Start; }
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SMLoc getEndLoc() const { return End; }
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virtual void print(raw_ostream &O) const {
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switch (Kind) {
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case k_Token:
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O << "Token: \"" << getToken() << "\"";
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break;
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case k_Register:
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O << "Register: " << getReg();
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break;
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case k_Immediate:
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O << "Immediate: \"" << *getImm() << "\"";
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break;
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case k_Memri: {
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// only manually print the size for non-negative values,
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// as the sign is inserted automatically.
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O << "Memri: \"" << getReg() << '+' << *getImm() << "\"";
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break;
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}
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}
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O << "\n";
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}
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};
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} // end anonymous namespace.
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// Auto-generated Match Functions
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/// Maps from the set of all register names to a register number.
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/// \note Generated by TableGen.
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static unsigned MatchRegisterName(StringRef Name);
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/// Maps from the set of all alternative registernames to a register number.
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/// \note Generated by TableGen.
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static unsigned MatchRegisterAltName(StringRef Name);
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bool AVRAsmParser::invalidOperand(SMLoc const &Loc,
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OperandVector const &Operands,
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uint64_t const &ErrorInfo) {
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SMLoc ErrorLoc = Loc;
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char const *Diag = 0;
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if (ErrorInfo != ~0U) {
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if (ErrorInfo >= Operands.size()) {
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Diag = "too few operands for instruction.";
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} else {
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AVROperand const &Op = (AVROperand const &)*Operands[ErrorInfo];
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// TODO: See if we can do a better error than just "invalid ...".
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if (Op.getStartLoc() != SMLoc()) {
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ErrorLoc = Op.getStartLoc();
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}
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}
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}
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if (!Diag) {
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Diag = "invalid operand for instruction";
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}
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return Error(ErrorLoc, Diag);
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}
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bool AVRAsmParser::missingFeature(llvm::SMLoc const &Loc,
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uint64_t const &ErrorInfo) {
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return Error(Loc, "instruction requires a CPU feature not currently enabled");
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}
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bool AVRAsmParser::emit(MCInst &Inst, SMLoc const &Loc, MCStreamer &Out) const {
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Inst.setLoc(Loc);
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Out.EmitInstruction(Inst, STI);
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return false;
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}
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bool AVRAsmParser::MatchAndEmitInstruction(SMLoc Loc, unsigned &Opcode,
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OperandVector &Operands,
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MCStreamer &Out, uint64_t &ErrorInfo,
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bool MatchingInlineAsm) {
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MCInst Inst;
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unsigned MatchResult =
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MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm);
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switch (MatchResult) {
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case Match_Success: return emit(Inst, Loc, Out);
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case Match_MissingFeature: return missingFeature(Loc, ErrorInfo);
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case Match_InvalidOperand: return invalidOperand(Loc, Operands, ErrorInfo);
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case Match_MnemonicFail: return Error(Loc, "invalid instruction");
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default: return true;
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}
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}
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/// Parses a register name using a given matching function.
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/// Checks for lowercase or uppercase if necessary.
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int AVRAsmParser::parseRegisterName(unsigned (*matchFn)(StringRef)) {
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StringRef Name = Parser.getTok().getString();
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int RegNum = matchFn(Name);
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// GCC supports case insensitive register names. Some of the AVR registers
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// are all lower case, some are all upper case but non are mixed. We prefer
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// to use the original names in the register definitions. That is why we
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// have to test both upper and lower case here.
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if (RegNum == AVR::NoRegister) {
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RegNum = matchFn(Name.lower());
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}
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if (RegNum == AVR::NoRegister) {
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RegNum = matchFn(Name.upper());
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}
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return RegNum;
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}
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int AVRAsmParser::parseRegisterName() {
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int RegNum = parseRegisterName(&MatchRegisterName);
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if (RegNum == AVR::NoRegister)
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RegNum = parseRegisterName(&MatchRegisterAltName);
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return RegNum;
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}
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int AVRAsmParser::parseRegister() {
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int RegNum = AVR::NoRegister;
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if (Parser.getTok().is(AsmToken::Identifier)) {
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// Check for register pair syntax
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if (Parser.getLexer().peekTok().is(AsmToken::Colon)) {
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Parser.Lex();
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Parser.Lex(); // Eat high (odd) register and colon
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if (Parser.getTok().is(AsmToken::Identifier)) {
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// Convert lower (even) register to DREG
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RegNum = toDREG(parseRegisterName());
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}
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} else {
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RegNum = parseRegisterName();
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}
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}
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return RegNum;
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}
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bool AVRAsmParser::tryParseRegisterOperand(OperandVector &Operands) {
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int RegNo = parseRegister();
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if (RegNo == AVR::NoRegister)
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return true;
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AsmToken const &T = Parser.getTok();
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Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc()));
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Parser.Lex(); // Eat register token.
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return false;
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}
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bool AVRAsmParser::tryParseExpression(OperandVector &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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if (!tryParseRelocExpression(Operands))
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return false;
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if ((Parser.getTok().getKind() == AsmToken::Plus ||
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Parser.getTok().getKind() == AsmToken::Minus) &&
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Parser.getLexer().peekTok().getKind() == AsmToken::Identifier) {
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// Don't handle this case - it should be split into two
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// separate tokens.
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return true;
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}
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// Parse (potentially inner) expression
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MCExpr const *Expression;
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if (getParser().parseExpression(Expression))
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return true;
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SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
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Operands.push_back(AVROperand::CreateImm(Expression, S, E));
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return false;
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}
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bool AVRAsmParser::tryParseRelocExpression(OperandVector &Operands) {
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bool isNegated = false;
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AVRMCExpr::VariantKind ModifierKind = AVRMCExpr::VK_AVR_None;
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SMLoc S = Parser.getTok().getLoc();
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// Check for sign
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AsmToken tokens[2];
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size_t ReadCount = Parser.getLexer().peekTokens(tokens);
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if (ReadCount == 2) {
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if ((tokens[0].getKind() == AsmToken::Identifier &&
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tokens[1].getKind() == AsmToken::LParen) ||
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(tokens[0].getKind() == AsmToken::LParen &&
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tokens[1].getKind() == AsmToken::Minus)) {
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AsmToken::TokenKind CurTok = Parser.getLexer().getKind();
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if (CurTok == AsmToken::Minus ||
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tokens[1].getKind() == AsmToken::Minus) {
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isNegated = true;
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} else {
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assert(CurTok == AsmToken::Plus);
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isNegated = false;
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}
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// Eat the sign
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if (CurTok == AsmToken::Minus || CurTok == AsmToken::Plus)
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Parser.Lex();
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}
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}
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// Check if we have a target specific modifier (lo8, hi8, &c)
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if (Parser.getTok().getKind() != AsmToken::Identifier ||
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Parser.getLexer().peekTok().getKind() != AsmToken::LParen) {
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// Not a reloc expr
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return true;
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}
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StringRef ModifierName = Parser.getTok().getString();
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ModifierKind = AVRMCExpr::getKindByName(ModifierName.str().c_str());
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if (ModifierKind != AVRMCExpr::VK_AVR_None) {
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Parser.Lex();
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Parser.Lex(); // Eat modifier name and parenthesis
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if (Parser.getTok().getString() == GENERATE_STUBS &&
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Parser.getTok().getKind() == AsmToken::Identifier) {
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std::string GSModName = ModifierName.str() + "_" + GENERATE_STUBS;
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ModifierKind = AVRMCExpr::getKindByName(GSModName.c_str());
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if (ModifierKind != AVRMCExpr::VK_AVR_None)
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Parser.Lex(); // Eat gs modifier name
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}
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} else {
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return Error(Parser.getTok().getLoc(), "unknown modifier");
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}
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if (tokens[1].getKind() == AsmToken::Minus ||
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tokens[1].getKind() == AsmToken::Plus) {
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Parser.Lex();
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assert(Parser.getTok().getKind() == AsmToken::LParen);
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Parser.Lex(); // Eat the sign and parenthesis
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}
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MCExpr const *InnerExpression;
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if (getParser().parseExpression(InnerExpression))
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return true;
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if (tokens[1].getKind() == AsmToken::Minus ||
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tokens[1].getKind() == AsmToken::Plus) {
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assert(Parser.getTok().getKind() == AsmToken::RParen);
|
|
Parser.Lex(); // Eat closing parenthesis
|
|
}
|
|
|
|
// If we have a modifier wrap the inner expression
|
|
assert(Parser.getTok().getKind() == AsmToken::RParen);
|
|
Parser.Lex(); // Eat closing parenthesis
|
|
|
|
MCExpr const *Expression = AVRMCExpr::create(ModifierKind, InnerExpression,
|
|
isNegated, getContext());
|
|
|
|
SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
Operands.push_back(AVROperand::CreateImm(Expression, S, E));
|
|
|
|
return false;
|
|
}
|
|
|
|
bool AVRAsmParser::parseOperand(OperandVector &Operands) {
|
|
LLVM_DEBUG(dbgs() << "parseOperand\n");
|
|
|
|
switch (getLexer().getKind()) {
|
|
default:
|
|
return Error(Parser.getTok().getLoc(), "unexpected token in operand");
|
|
|
|
case AsmToken::Identifier:
|
|
// Try to parse a register, if it fails,
|
|
// fall through to the next case.
|
|
if (!tryParseRegisterOperand(Operands)) {
|
|
return false;
|
|
}
|
|
LLVM_FALLTHROUGH;
|
|
case AsmToken::LParen:
|
|
case AsmToken::Integer:
|
|
case AsmToken::Dot:
|
|
return tryParseExpression(Operands);
|
|
case AsmToken::Plus:
|
|
case AsmToken::Minus: {
|
|
// If the sign preceeds a number, parse the number,
|
|
// otherwise treat the sign a an independent token.
|
|
switch (getLexer().peekTok().getKind()) {
|
|
case AsmToken::Integer:
|
|
case AsmToken::BigNum:
|
|
case AsmToken::Identifier:
|
|
case AsmToken::Real:
|
|
if (!tryParseExpression(Operands))
|
|
return false;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
// Treat the token as an independent token.
|
|
Operands.push_back(AVROperand::CreateToken(Parser.getTok().getString(),
|
|
Parser.getTok().getLoc()));
|
|
Parser.Lex(); // Eat the token.
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// Could not parse operand
|
|
return true;
|
|
}
|
|
|
|
OperandMatchResultTy
|
|
AVRAsmParser::parseMemriOperand(OperandVector &Operands) {
|
|
LLVM_DEBUG(dbgs() << "parseMemriOperand()\n");
|
|
|
|
SMLoc E, S;
|
|
MCExpr const *Expression;
|
|
int RegNo;
|
|
|
|
// Parse register.
|
|
{
|
|
RegNo = parseRegister();
|
|
|
|
if (RegNo == AVR::NoRegister)
|
|
return MatchOperand_ParseFail;
|
|
|
|
S = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
Parser.Lex(); // Eat register token.
|
|
}
|
|
|
|
// Parse immediate;
|
|
{
|
|
if (getParser().parseExpression(Expression))
|
|
return MatchOperand_ParseFail;
|
|
|
|
E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
|
|
}
|
|
|
|
Operands.push_back(AVROperand::CreateMemri(RegNo, Expression, S, E));
|
|
|
|
return MatchOperand_Success;
|
|
}
|
|
|
|
bool AVRAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
|
|
SMLoc &EndLoc) {
|
|
StartLoc = Parser.getTok().getLoc();
|
|
RegNo = parseRegister();
|
|
EndLoc = Parser.getTok().getLoc();
|
|
|
|
return (RegNo == AVR::NoRegister);
|
|
}
|
|
|
|
void AVRAsmParser::eatComma() {
|
|
if (getLexer().is(AsmToken::Comma)) {
|
|
Parser.Lex();
|
|
} else {
|
|
// GCC allows commas to be omitted.
|
|
}
|
|
}
|
|
|
|
bool AVRAsmParser::ParseInstruction(ParseInstructionInfo &Info,
|
|
StringRef Mnemonic, SMLoc NameLoc,
|
|
OperandVector &Operands) {
|
|
Operands.push_back(AVROperand::CreateToken(Mnemonic, NameLoc));
|
|
|
|
bool first = true;
|
|
while (getLexer().isNot(AsmToken::EndOfStatement)) {
|
|
if (!first) eatComma();
|
|
|
|
first = false;
|
|
|
|
auto MatchResult = MatchOperandParserImpl(Operands, Mnemonic);
|
|
|
|
if (MatchResult == MatchOperand_Success) {
|
|
continue;
|
|
}
|
|
|
|
if (MatchResult == MatchOperand_ParseFail) {
|
|
SMLoc Loc = getLexer().getLoc();
|
|
Parser.eatToEndOfStatement();
|
|
|
|
return Error(Loc, "failed to parse register and immediate pair");
|
|
}
|
|
|
|
if (parseOperand(Operands)) {
|
|
SMLoc Loc = getLexer().getLoc();
|
|
Parser.eatToEndOfStatement();
|
|
return Error(Loc, "unexpected token in argument list");
|
|
}
|
|
}
|
|
Parser.Lex(); // Consume the EndOfStatement
|
|
return false;
|
|
}
|
|
|
|
bool AVRAsmParser::ParseDirective(llvm::AsmToken DirectiveID) {
|
|
StringRef IDVal = DirectiveID.getIdentifier();
|
|
if (IDVal.lower() == ".long") {
|
|
parseLiteralValues(SIZE_LONG, DirectiveID.getLoc());
|
|
} else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
|
|
parseLiteralValues(SIZE_WORD, DirectiveID.getLoc());
|
|
} else if (IDVal.lower() == ".byte") {
|
|
parseLiteralValues(1, DirectiveID.getLoc());
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool AVRAsmParser::parseLiteralValues(unsigned SizeInBytes, SMLoc L) {
|
|
MCAsmParser &Parser = getParser();
|
|
AVRMCELFStreamer &AVRStreamer =
|
|
static_cast<AVRMCELFStreamer &>(Parser.getStreamer());
|
|
AsmToken Tokens[2];
|
|
size_t ReadCount = Parser.getLexer().peekTokens(Tokens);
|
|
if (ReadCount == 2 && Parser.getTok().getKind() == AsmToken::Identifier &&
|
|
Tokens[0].getKind() == AsmToken::Minus &&
|
|
Tokens[1].getKind() == AsmToken::Identifier) {
|
|
MCSymbol *Symbol = getContext().getOrCreateSymbol(".text");
|
|
AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L,
|
|
AVRMCExpr::VK_AVR_None);
|
|
return false;
|
|
}
|
|
|
|
if (Parser.getTok().getKind() == AsmToken::Identifier &&
|
|
Parser.getLexer().peekTok().getKind() == AsmToken::LParen) {
|
|
StringRef ModifierName = Parser.getTok().getString();
|
|
AVRMCExpr::VariantKind ModifierKind =
|
|
AVRMCExpr::getKindByName(ModifierName.str().c_str());
|
|
if (ModifierKind != AVRMCExpr::VK_AVR_None) {
|
|
Parser.Lex();
|
|
Parser.Lex(); // Eat the modifier and parenthesis
|
|
} else {
|
|
return Error(Parser.getTok().getLoc(), "unknown modifier");
|
|
}
|
|
MCSymbol *Symbol =
|
|
getContext().getOrCreateSymbol(Parser.getTok().getString());
|
|
AVRStreamer.EmitValueForModiferKind(Symbol, SizeInBytes, L, ModifierKind);
|
|
return false;
|
|
}
|
|
|
|
auto parseOne = [&]() -> bool {
|
|
const MCExpr *Value;
|
|
if (Parser.parseExpression(Value))
|
|
return true;
|
|
Parser.getStreamer().EmitValue(Value, SizeInBytes, L);
|
|
return false;
|
|
};
|
|
return (parseMany(parseOne));
|
|
}
|
|
|
|
extern "C" void LLVMInitializeAVRAsmParser() {
|
|
RegisterMCAsmParser<AVRAsmParser> X(getTheAVRTarget());
|
|
}
|
|
|
|
#define GET_REGISTER_MATCHER
|
|
#define GET_MATCHER_IMPLEMENTATION
|
|
#include "AVRGenAsmMatcher.inc"
|
|
|
|
// Uses enums defined in AVRGenAsmMatcher.inc
|
|
unsigned AVRAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
|
|
unsigned ExpectedKind) {
|
|
AVROperand &Op = static_cast<AVROperand &>(AsmOp);
|
|
MatchClassKind Expected = static_cast<MatchClassKind>(ExpectedKind);
|
|
|
|
// If need be, GCC converts bare numbers to register names
|
|
// It's ugly, but GCC supports it.
|
|
if (Op.isImm()) {
|
|
if (MCConstantExpr const *Const = dyn_cast<MCConstantExpr>(Op.getImm())) {
|
|
int64_t RegNum = Const->getValue();
|
|
std::ostringstream RegName;
|
|
RegName << "r" << RegNum;
|
|
RegNum = MatchRegisterName(RegName.str().c_str());
|
|
if (RegNum != AVR::NoRegister) {
|
|
Op.makeReg(RegNum);
|
|
if (validateOperandClass(Op, Expected) == Match_Success) {
|
|
return Match_Success;
|
|
}
|
|
}
|
|
// Let the other quirks try their magic.
|
|
}
|
|
}
|
|
|
|
if (Op.isReg()) {
|
|
// If the instruction uses a register pair but we got a single, lower
|
|
// register we perform a "class cast".
|
|
if (isSubclass(Expected, MCK_DREGS)) {
|
|
unsigned correspondingDREG = toDREG(Op.getReg());
|
|
|
|
if (correspondingDREG != AVR::NoRegister) {
|
|
Op.makeReg(correspondingDREG);
|
|
return validateOperandClass(Op, Expected);
|
|
}
|
|
}
|
|
}
|
|
return Match_InvalidOperand;
|
|
}
|