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7eaac1c18c
There is an issue with early CSE hitting an assert, so temporarily
remove the pass from the Arm backend.
Bug: https://bugs.llvm.org/show_bug.cgi?id=41081
Differential Revision: https://reviews.llvm.org/D59410
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356259 91177308-0d34-0410-b5e6-96231b3b80d8
150 lines
6.3 KiB
LLVM
150 lines
6.3 KiB
LLVM
; RUN: llc -mtriple=arm -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | FileCheck %s
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; REQUIRES: asserts
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; CHECK: ModulePass Manager
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; CHECK: Pre-ISel Intrinsic Lowering
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; CHECK: FunctionPass Manager
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; CHECK: Expand Atomic instructions
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; CHECK: Simplify the CFG
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; CHECK: Dominator Tree Construction
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; CHECK: Basic Alias Analysis (stateless AA impl)
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; CHECK: Module Verifier
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; CHECK: Natural Loop Information
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; CHECK: Canonicalize natural loops
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; CHECK: Scalar Evolution Analysis
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; CHECK: Loop Pass Manager
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; CHECK: Induction Variable Users
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; CHECK: Loop Strength Reduction
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; CHECK: Basic Alias Analysis (stateless AA impl)
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; CHECK: Function Alias Analysis Results
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; CHECK: Merge contiguous icmps into a memcmp
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; CHECK: Expand memcmp() to load/stores
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; CHECK: Lower Garbage Collection Instructions
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; CHECK: Shadow Stack GC Lowering
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; CHECK: Remove unreachable blocks from the CFG
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; CHECK: Dominator Tree Construction
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; CHECK: Natural Loop Information
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; CHECK: Branch Probability Analysis
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; CHECK: Block Frequency Analysis
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; CHECK: Constant Hoisting
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; CHECK: Partially inline calls to library functions
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; CHECK: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
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; CHECK: Scalarize Masked Memory Intrinsics
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; CHECK: Expand reduction intrinsics
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; CHECK: Dominator Tree Construction
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; CHECK: Natural Loop Information
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; CHECK: Scalar Evolution Analysis
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; CHECK: Basic Alias Analysis (stateless AA impl)
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; CHECK: Function Alias Analysis Results
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; CHECK: Loop Pass Manager
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; CHECK: Transform loops to use DSP intrinsics
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; CHECK: Interleaved Access Pass
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; CHECK: ARM IR optimizations
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; CHECK: Dominator Tree Construction
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; CHECK: Natural Loop Information
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; CHECK: CodeGen Prepare
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; CHECK: Rewrite Symbols
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; CHECK: FunctionPass Manager
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; CHECK: Dominator Tree Construction
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; CHECK: Exception handling preparation
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; CHECK: Merge internal globals
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; CHECK: Safe Stack instrumentation pass
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; CHECK: Insert stack protectors
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; CHECK: Module Verifier
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; CHECK: Dominator Tree Construction
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; CHECK: Basic Alias Analysis (stateless AA impl)
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; CHECK: Function Alias Analysis Results
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; CHECK: Natural Loop Information
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; CHECK: Branch Probability Analysis
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; CHECK: ARM Instruction Selection
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; CHECK: Expand ISel Pseudo-instructions
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; CHECK: Early Tail Duplication
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; CHECK: Optimize machine instruction PHIs
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; CHECK: Slot index numbering
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; CHECK: Merge disjoint stack slots
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; CHECK: Local Stack Slot Allocation
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; CHECK: Remove dead machine instructions
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; CHECK: MachineDominator Tree Construction
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; CHECK: Machine Natural Loop Construction
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; CHECK: Early Machine Loop Invariant Code Motion
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; CHECK: Machine Common Subexpression Elimination
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; CHECK: MachinePostDominator Tree Construction
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; CHECK: Machine Block Frequency Analysis
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; CHECK: Machine code sinking
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; CHECK: Peephole Optimizations
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; CHECK: Remove dead machine instructions
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; CHECK: ARM MLA / MLS expansion pass
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; CHECK: ARM pre- register allocation load / store optimization pass
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; CHECK: ARM A15 S->D optimizer
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; CHECK: Detect Dead Lanes
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; CHECK: Process Implicit Definitions
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; CHECK: Remove unreachable machine basic blocks
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; CHECK: Live Variable Analysis
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; CHECK: MachineDominator Tree Construction
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; CHECK: Machine Natural Loop Construction
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; CHECK: Eliminate PHI nodes for register allocation
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; CHECK: Two-Address instruction pass
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; CHECK: Slot index numbering
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; CHECK: Live Interval Analysis
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; CHECK: Simple Register Coalescing
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; CHECK: Rename Disconnected Subregister Components
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; CHECK: Machine Instruction Scheduler
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; CHECK: Machine Block Frequency Analysis
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; CHECK: Debug Variable Analysis
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; CHECK: Live Stack Slot Analysis
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; CHECK: Virtual Register Map
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; CHECK: Live Register Matrix
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; CHECK: Bundle Machine CFG Edges
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; CHECK: Spill Code Placement Analysis
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; CHECK: Lazy Machine Block Frequency Analysis
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; CHECK: Machine Optimization Remark Emitter
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; CHECK: Greedy Register Allocator
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; CHECK: Virtual Register Rewriter
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; CHECK: Stack Slot Coloring
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; CHECK: Machine Copy Propagation Pass
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; CHECK: Machine Loop Invariant Code Motion
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; CHECK: PostRA Machine Sink
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; CHECK: Machine Block Frequency Analysis
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; CHECK: MachinePostDominator Tree Construction
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; CHECK: Lazy Machine Block Frequency Analysis
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; CHECK: Machine Optimization Remark Emitter
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; CHECK: Shrink Wrapping analysis
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; CHECK: Prologue/Epilogue Insertion & Frame Finalization
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; CHECK: Control Flow Optimizer
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; CHECK: Tail Duplication
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; CHECK: Machine Copy Propagation Pass
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; CHECK: Post-RA pseudo instruction expansion pass
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; CHECK: ARM load / store optimization pass
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; CHECK: ReachingDefAnalysis
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; CHECK: ARM Execution Domain Fix
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; CHECK: BreakFalseDeps
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; CHECK: ARM pseudo instruction expansion pass
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; CHECK: Thumb2 instruction size reduce pass
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; CHECK: MachineDominator Tree Construction
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; CHECK: Machine Natural Loop Construction
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; CHECK: Machine Block Frequency Analysis
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; CHECK: If Converter
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; CHECK: Thumb IT blocks insertion pass
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; CHECK: MachineDominator Tree Construction
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; CHECK: Machine Natural Loop Construction
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; CHECK: Post RA top-down list latency scheduler
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; CHECK: Analyze Machine Code For Garbage Collection
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; CHECK: Machine Block Frequency Analysis
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; CHECK: MachinePostDominator Tree Construction
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; CHECK: Branch Probability Basic Block Placement
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; CHECK: Thumb2 instruction size reduce pass
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; CHECK: Unpack machine instruction bundles
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; CHECK: optimise barriers pass
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; CHECK: ARM constant island placement and branch shortening pass
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; CHECK: Contiguously Lay Out Funclets
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; CHECK: StackMap Liveness Analysis
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; CHECK: Live DEBUG_VALUE analysis
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; CHECK: Insert fentry calls
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; CHECK: Insert XRay ops
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; CHECK: Implement the 'patchable-function' attribute
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; CHECK: Lazy Machine Block Frequency Analysis
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; CHECK: Machine Optimization Remark Emitter
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; CHECK: ARM Assembly Printer
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; CHECK: Free MachineFunction
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