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78f5683a63
The SchedModel allows the addition of ReadAdvances to express that certain operands of the instructions are needed at a later point than the others. RegAlloc may add pseudo operands that are not part of the instruction descriptor, and therefore cannot have any read advance entries. This meant that in some cases the desired read advance was nullified by such a pseudo operand, which still had the original latency. This patch fixes this by making sure that such pseudo operands get a zero latency during DAG construction. Review: Matthias Braun, Ulrich Weigand. https://reviews.llvm.org/D49671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345606 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
751 B
LLVM
23 lines
751 B
LLVM
; Tests for the two-address instruction pass.
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 -arm-atomic-cfg-tidy=0 %s -o - | FileCheck %s
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define void @PR13378() nounwind {
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; This was orriginally a crasher trying to schedule the instructions.
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; CHECK-LABEL: PR13378:
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; CHECK: vmov.i32
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; CHECK-NEXT: vld1.32
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; CHECK-NEXT: vst1.32
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; CHECK-NEXT: vst1.32
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; CHECK-NEXT: vmov.f32
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; CHECK-NEXT: vmov.f32
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; CHECK-NEXT: vst1.32
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entry:
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%0 = load <4 x float>, <4 x float>* undef, align 4
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store <4 x float> zeroinitializer, <4 x float>* undef, align 4
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store <4 x float> %0, <4 x float>* undef, align 4
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%1 = insertelement <4 x float> %0, float 1.000000e+00, i32 3
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store <4 x float> %1, <4 x float>* undef, align 4
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unreachable
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}
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