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287a3ef3c9
HexagonGenMux would collapse pairs of predicated transfers if it assumed that the predicated .new forms cannot be created. Turns out that generating mux is preferable in almost all cases. Introduce an option -hexagon-gen-mux-threshold that controls the minimum distance between the instruction defining the predicate and the later of the two transfers. If the distance is closer than the threshold, mux will not be generated. Set the threshold to 0 by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@328346 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
1.8 KiB
LLVM
90 lines
1.8 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-gen-mux-threshold=4 < %s | FileCheck %s
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; Generate various cmpb instruction followed by if (p0) .. if (!p0)...
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target triple = "hexagon"
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@Enum_global = external global i8
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define i32 @Func_3(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp eq i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3b(i32) nounwind readonly {
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entry:
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; CHECK-NOT: mux
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%1 = load i8, i8* @Enum_global, align 1
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%2 = trunc i32 %0 to i8
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%cmp = icmp ne i8 %1, %2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3c(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp eq i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3d(i32) nounwind readonly {
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entry:
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; CHECK-NOT: mux
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%1 = load i8, i8* @Enum_global, align 1
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%2 = trunc i32 %0 to i8
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%cmp = icmp eq i8 %1, %2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3e(i32) nounwind readonly {
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entry:
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; CHECK-NOT: mux
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%1 = load i8, i8* @Enum_global, align 1
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%2 = trunc i32 %0 to i8
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%cmp = icmp eq i8 %1, %2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3f(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp ugt i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3g(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 255
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%cmp = icmp ult i32 %conv, 3
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3h(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 254
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%cmp = icmp ult i32 %conv, 2
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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define i32 @Func_3i(i32) nounwind readnone {
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entry:
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; CHECK-NOT: mux
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%conv = and i32 %0, 254
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%cmp = icmp ugt i32 %conv, 1
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%selv = zext i1 %cmp to i32
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ret i32 %selv
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}
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