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History

Matt Arsenault 4710131927 MIR: Freeze reserved regs after parsing everything

The AMDGPU implementation of getReservedRegs depends on
MachineFunctionInfo fields that are parsed from the YAML section. This
was reserving the wrong register since it was setting the reserved
regs before parsing the correct one.

Some tests were relying on the default reserved set for the assumed
default calling convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357083 91177308-0d34-0410-b5e6-96231b3b80d8

2019-03-27 16:12:26 +00:00

AArch64

MIR: Validate LLT types when parsing

2019-02-04 22:59:56 +00:00

AMDGPU

MIR: Freeze reserved regs after parsing everything

2019-03-27 16:12:26 +00:00

ARM

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Generic

[codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL

2018-10-01 21:59:45 +00:00

Hexagon

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

NVPTX

[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.

2018-01-10 00:56:48 +00:00

PowerPC

[Power9] Allow gpr callee saved spills in prologue to vectors registers

2018-11-09 16:36:24 +00:00

WebAssembly

[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)

2018-05-08 02:02:50 +00:00

X86

[X86] Add FPCW as an implicit use on floating point load instructions.

2019-02-08 20:50:09 +00:00

README

Add README describing the intention of test/CodeGen/MIR

2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.