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e2dd6e1812
MIPS ISAs start to support third operand for the `rdhwr` instruction starting from Revision 6. But LLVM generates assembler code with three-operands version of this instruction on any MIPS64 ISA. The third operand is always zero, so in case of direct code generation we get correct code. This patch fixes the bug by adding an instruction alias. The same alias already exists for 32-bit ISA. Ideally, we also need to reject three-operands version of the `rdhwr` instruction in an assembler code if ISA revision is less than 6. That is a task for a separate patch. This fixes PR38861 (https://bugs.llvm.org/show_bug.cgi?id=38861) Differential revision: https://reviews.llvm.org/D51773 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341919 91177308-0d34-0410-b5e6-96231b3b80d8
158 lines
5.7 KiB
LLVM
158 lines
5.7 KiB
LLVM
; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler \
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; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC32
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; RUN: llc -mtriple=mips64el-- -disable-mips-delay-filler \
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; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC64
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; RUN: llc -mtriple=mipsel-- -mattr=+micromips -disable-mips-delay-filler \
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; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=MM
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; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler \
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; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC32
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; RUN: llc -mtriple=mips64el-- -disable-mips-delay-filler \
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; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC64
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; RUN: llc -mtriple=mipsel-- -disable-mips-delay-filler -mips-fix-global-base-reg=false \
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; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=STATICGP32
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; RUN: llc -mtriple=mips64el-- -disable-mips-delay-filler -mips-fix-global-base-reg=false \
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; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=STATICGP64
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@t1 = thread_local global i32 0, align 4
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define i32 @f1() nounwind {
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entry:
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%tmp = load i32, i32* @t1, align 4
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ret i32 %tmp
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; PIC32-LABEL: f1:
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; PIC32-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
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; PIC32-DAG: addiu $4, $[[R0]], %tlsgd(t1)
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; PIC32-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
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; PIC32-DAG: jalr $25
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; PIC32-DAG: lw $2, 0($2)
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; PIC64-LABEL: f1:
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; PIC64-DAG: daddiu $[[R0:[a-z0-9]+]], $1, %lo(%neg(%gp_rel(f1)))
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; PIC64-DAG: daddiu $4, $[[R0]], %tlsgd(t1)
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; PIC64-DAG: ld $25, %call16(__tls_get_addr)($[[R0]])
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; PIC64-DAG: jalr $25
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; PIC64-DAG: lw $2, 0($2)
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; MM-LABEL: f1:
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; MM-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
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; MM-DAG: addiu $4, $[[R0]], %tlsgd(t1)
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; MM-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
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; MM-DAG: move $gp, $2
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; MM-DAG: jalr $25
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; MM-DAG: lw16 $2, 0($2)
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; STATIC32-LABEL: f1:
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; STATIC32: lui $[[R0:[0-9]+]], %tprel_hi(t1)
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; STATIC32: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
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; STATIC32: rdhwr $3, $29{{$}}
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; STATIC32: addu $[[R2:[0-9]+]], $3, $[[R1]]
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; STATIC32: lw $2, 0($[[R2]])
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; STATIC64-LABEL: f1:
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; STATIC64: lui $[[R0:[0-9]+]], %tprel_hi(t1)
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; STATIC64: daddiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
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; STATIC64: rdhwr $3, $29{{$}}
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; STATIC64: daddu $[[R2:[0-9]+]], $3, $[[R0]]
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; STATIC64: lw $2, 0($[[R2]])
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}
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@t2 = external thread_local global i32
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define i32 @f2() nounwind {
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entry:
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%tmp = load i32, i32* @t2, align 4
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ret i32 %tmp
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; PIC32-LABEL: f2:
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; PIC32-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
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; PIC32-DAG: addiu $4, $[[R0]], %tlsgd(t2)
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; PIC32-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
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; PIC32-DAG: jalr $25
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; PIC32-DAG: lw $2, 0($2)
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; PIC64-LABEL: f2:
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; PIC64-DAG: daddiu $[[R0:[a-z0-9]+]], $1, %lo(%neg(%gp_rel(f2)))
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; PIC64-DAG: daddiu $4, $[[R0]], %tlsgd(t2)
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; PIC64-DAG: ld $25, %call16(__tls_get_addr)($[[R0]])
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; PIC64-DAG: jalr $25
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; PIC64-DAG: lw $2, 0($2)
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; MM-LABEL: f2:
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; MM-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
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; MM-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
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; MM-DAG: addiu $4, $[[R0]], %tlsgd(t2)
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; MM-DAG: jalr $25
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; MM-DAG: lw16 $2, 0($2)
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; STATICGP32-LABEL: f2:
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; STATICGP32: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
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; STATICGP32: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
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; STATICGP32: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]])
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; STATICGP64-LABEL: f2:
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; STATICGP64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
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; STATICGP64: daddiu $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
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; STATICGP64: ld $1, %gottprel(t2)($[[GP]])
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; STATIC32-LABEL: f2:
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; STATIC32: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
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; STATIC32: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
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; STATIC32: rdhwr $3, $29{{$}}
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; STATIC32: lw $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
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; STATIC32: addu $[[R1:[0-9]+]], $3, $[[R0]]
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; STATIC32: lw $2, 0($[[R1]])
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; STATIC64-LABEL: f2:
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; STATIC64: lui $[[R0:[0-9]+]], %hi(%neg(%gp_rel(f2)))
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; STATIC64: daddiu $[[GP:[0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f2)))
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; STATIC64: rdhwr $3, $29{{$}}
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; STATIC64: ld $[[R0:[0-9]+]], %gottprel(t2)($[[GP]])
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; STATIC64: daddu $[[R1:[0-9]+]], $3, $[[R0]]
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; STATIC64: lw $2, 0($[[R1]])
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}
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@f3.i = internal thread_local unnamed_addr global i32 1, align 4
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define i32 @f3() nounwind {
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entry:
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; PIC32-LABEL: f3:
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; PIC32: addu $[[R0:[a-z0-9]+]], $2, $25
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; PIC32: addiu $4, $[[R0]], %tlsldm(f3.i)
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; PIC32: lw $25, %call16(__tls_get_addr)($[[R0]])
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; PIC32: jalr $25
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; PIC32: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
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; PIC32: addu $[[R1:[0-9]+]], $[[R0]], $2
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; PIC32: lw $[[R3:[0-9]+]], %dtprel_lo(f3.i)($[[R1]])
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; PIC32: addiu $[[R3]], $[[R3]], 1
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; PIC32: sw $[[R3]], %dtprel_lo(f3.i)($[[R1]])
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; PIC64-LABEL: f3:
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; PIC64: lui $[[R0:[a-z0-9]+]], %hi(%neg(%gp_rel(f3)))
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; PIC64: daddu $[[R0]], $[[R0]], $25
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; PIC64: daddiu $[[R1:[a-z0-9]+]], $[[R0]], %lo(%neg(%gp_rel(f3)))
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; PIC64: daddiu $4, $[[R1]], %tlsldm(f3.i)
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; PIC64: ld $25, %call16(__tls_get_addr)($[[R1]])
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; PIC64: jalr $25
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; PIC64: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
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; PIC64: daddu $[[R1:[0-9]+]], $[[R0]], $2
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; PIC64: lw $[[R2:[0-9]+]], %dtprel_lo(f3.i)($[[R1]])
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; PIC64: addiu $[[R2]], $[[R2]], 1
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; PIC64: sw $[[R2]], %dtprel_lo(f3.i)($[[R1]])
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; MM-LABEL: f3:
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; MM: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
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; MM: jalr $25
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; MM: lui $[[R0:[0-9]+]], %dtprel_hi(f3.i)
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; MM: addu16 $[[R1:[0-9]+]], $[[R0]], $2
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; MM: lw ${{[0-9]+}}, %dtprel_lo(f3.i)($[[R1]])
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%0 = load i32, i32* @f3.i, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @f3.i, align 4
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ret i32 %inc
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}
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