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8f7dc5cb4e
- Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345532 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.6 KiB
LLVM
47 lines
1.6 KiB
LLVM
; RUN: llc -relocation-model=static -verify-machineinstrs -O0 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s
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; RUN: llc -relocation-model=static -verify-machineinstrs -O1 < %s -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s
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; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=ppc32-- -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s
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target triple = "powerpc64-unknown-linux-gnu"
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@a = thread_local global i32 0, align 4
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;OPT0-LABEL: localexec:
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;OPT1-LABEL: localexec:
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define i32 @localexec() nounwind {
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entry:
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;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha
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;OPT0-NEXT: addi [[REG2:[0-9]+]], [[REG1]], a@tprel@l
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;OPT0-NEXT: li [[REG3:[0-9]+]], 42
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;OPT0: stw [[REG3]], 0([[REG2]])
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;OPT1: addis [[REG1:[0-9]+]], 13, a@tprel@ha
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;OPT1-NEXT: li [[REG3:[0-9]+]], 42
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;OPT1: stw [[REG3]], a@tprel@l([[REG1]])
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store i32 42, i32* @a, align 4
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ret i32 0
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}
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; Test correct assembly code generation for thread-local storage
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; using the initial-exec model.
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@a2 = external thread_local global i32
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define signext i32 @main2() nounwind {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32, i32* @a2, align 4
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ret i32 %0
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}
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; OPT1-LABEL: main2:
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; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha
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; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
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; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls
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;OPT0-PPC32-LABEL: main2:
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;OPT0-PPC32: li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_@l
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;OPT0-PPC32: addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_@ha
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;OPT0-PPC32: lwz [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]])
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;OPT0-PPC32: add 3, [[REG2]], a2@tls
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