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5816be49d6
This requires a little extra work due tothe fact i32 is not a legal type. When call lowering happens post-legalisation (e.g. when an intrinsic was inserted during legalisation). A bitcast from f32 to i32 can't be introduced. This is similar to the challenges with RV32D. To handle this, we introduce target-specific DAG nodes that perform bitcast+anyext for f32->i64 and trunc+bitcast for i64->f32. Differential Revision: https://reviews.llvm.org/D53235 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352807 91177308-0d34-0410-b5e6-96231b3b80d8
350 lines
9.1 KiB
LLVM
350 lines
9.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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define i32 @fcmp_false(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_false:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: mv a0, zero
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_false:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: mv a0, zero
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; RV64IF-NEXT: ret
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%1 = fcmp false float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_oeq(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_oeq:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: feq.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_oeq:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: feq.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp oeq float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ogt(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_ogt:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: flt.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_ogt:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: flt.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp ogt float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_oge(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_oge:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fle.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_oge:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fle.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp oge float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_olt(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_olt:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: flt.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_olt:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: flt.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp olt float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ole(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_ole:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fle.s a0, ft1, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_ole:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fle.s a0, ft1, ft0
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; RV64IF-NEXT: ret
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%1 = fcmp ole float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_one(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_one:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: feq.s a0, ft1, ft1
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; RV32IF-NEXT: feq.s a1, ft0, ft0
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; RV32IF-NEXT: and a0, a1, a0
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; RV32IF-NEXT: feq.s a1, ft0, ft1
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; RV32IF-NEXT: not a1, a1
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; RV32IF-NEXT: seqz a0, a0
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; RV32IF-NEXT: xori a0, a0, 1
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; RV32IF-NEXT: and a0, a1, a0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_one:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: feq.s a0, ft1, ft1
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; RV64IF-NEXT: feq.s a1, ft0, ft0
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; RV64IF-NEXT: and a0, a1, a0
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; RV64IF-NEXT: feq.s a1, ft0, ft1
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; RV64IF-NEXT: not a1, a1
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; RV64IF-NEXT: seqz a0, a0
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; RV64IF-NEXT: xori a0, a0, 1
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; RV64IF-NEXT: and a0, a1, a0
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; RV64IF-NEXT: ret
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%1 = fcmp one float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ord(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_ord:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: feq.s a1, ft0, ft0
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: feq.s a0, ft0, ft0
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; RV32IF-NEXT: and a0, a0, a1
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; RV32IF-NEXT: seqz a0, a0
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; RV32IF-NEXT: xori a0, a0, 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_ord:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: feq.s a1, ft0, ft0
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: feq.s a0, ft0, ft0
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; RV64IF-NEXT: and a0, a0, a1
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; RV64IF-NEXT: seqz a0, a0
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; RV64IF-NEXT: xori a0, a0, 1
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; RV64IF-NEXT: ret
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%1 = fcmp ord float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ueq(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_ueq:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: feq.s a0, ft1, ft0
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; RV32IF-NEXT: feq.s a1, ft0, ft0
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; RV32IF-NEXT: feq.s a2, ft1, ft1
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; RV32IF-NEXT: and a1, a2, a1
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; RV32IF-NEXT: seqz a1, a1
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; RV32IF-NEXT: or a0, a0, a1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_ueq:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: feq.s a0, ft1, ft0
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; RV64IF-NEXT: feq.s a1, ft0, ft0
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; RV64IF-NEXT: feq.s a2, ft1, ft1
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; RV64IF-NEXT: and a1, a2, a1
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; RV64IF-NEXT: seqz a1, a1
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; RV64IF-NEXT: or a0, a0, a1
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; RV64IF-NEXT: ret
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%1 = fcmp ueq float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ugt(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_ugt:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fle.s a0, ft1, ft0
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; RV32IF-NEXT: xori a0, a0, 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_ugt:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fle.s a0, ft1, ft0
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; RV64IF-NEXT: xori a0, a0, 1
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; RV64IF-NEXT: ret
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%1 = fcmp ugt float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_uge(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_uge:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: flt.s a0, ft1, ft0
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; RV32IF-NEXT: xori a0, a0, 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_uge:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: flt.s a0, ft1, ft0
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; RV64IF-NEXT: xori a0, a0, 1
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; RV64IF-NEXT: ret
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%1 = fcmp uge float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ult(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_ult:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fle.s a0, ft1, ft0
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; RV32IF-NEXT: xori a0, a0, 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_ult:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fle.s a0, ft1, ft0
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; RV64IF-NEXT: xori a0, a0, 1
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; RV64IF-NEXT: ret
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%1 = fcmp ult float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_ule(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_ule:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: flt.s a0, ft1, ft0
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; RV32IF-NEXT: xori a0, a0, 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_ule:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: flt.s a0, ft1, ft0
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; RV64IF-NEXT: xori a0, a0, 1
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; RV64IF-NEXT: ret
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%1 = fcmp ule float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_une(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_une:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: feq.s a0, ft1, ft0
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; RV32IF-NEXT: xori a0, a0, 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_une:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: feq.s a0, ft1, ft0
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; RV64IF-NEXT: xori a0, a0, 1
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; RV64IF-NEXT: ret
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%1 = fcmp une float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_uno(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_uno:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: feq.s a1, ft0, ft0
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: feq.s a0, ft0, ft0
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; RV32IF-NEXT: and a0, a0, a1
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; RV32IF-NEXT: seqz a0, a0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_uno:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: feq.s a1, ft0, ft0
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: feq.s a0, ft0, ft0
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; RV64IF-NEXT: and a0, a0, a1
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; RV64IF-NEXT: seqz a0, a0
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; RV64IF-NEXT: ret
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%1 = fcmp uno float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fcmp_true(float %a, float %b) nounwind {
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; RV32IF-LABEL: fcmp_true:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi a0, zero, 1
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcmp_true:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: addi a0, zero, 1
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; RV64IF-NEXT: ret
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%1 = fcmp true float %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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