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810e8672a4
For targets where i32 is not a legal type (e.g. 64-bit RISC-V), LegalizeIntegerTypes must promote the operand. Differential Revision: https://reviews.llvm.org/D53279 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347978 91177308-0d34-0410-b5e6-96231b3b80d8
153 lines
4.3 KiB
LLVM
153 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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declare void @notdead(i8*)
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declare i8* @llvm.frameaddress(i32)
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declare i8* @llvm.returnaddress(i32)
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define i8* @test_frameaddress_0() nounwind {
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; RV32I-LABEL: test_frameaddress_0:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: mv a0, s0
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_frameaddress_0:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sd s0, 0(sp)
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; RV64I-NEXT: addi s0, sp, 16
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; RV64I-NEXT: mv a0, s0
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; RV64I-NEXT: ld s0, 0(sp)
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call i8* @llvm.frameaddress(i32 0)
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ret i8* %1
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}
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define i8* @test_frameaddress_2() nounwind {
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; RV32I-LABEL: test_frameaddress_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: lw a0, -8(s0)
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; RV32I-NEXT: lw a0, -8(a0)
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_frameaddress_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sd s0, 0(sp)
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; RV64I-NEXT: addi s0, sp, 16
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; RV64I-NEXT: ld a0, -16(s0)
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; RV64I-NEXT: ld a0, -16(a0)
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; RV64I-NEXT: ld s0, 0(sp)
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call i8* @llvm.frameaddress(i32 2)
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ret i8* %1
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}
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define i8* @test_frameaddress_3_alloca() nounwind {
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; RV32I-LABEL: test_frameaddress_3_alloca:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -112
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; RV32I-NEXT: sw ra, 108(sp)
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; RV32I-NEXT: sw s0, 104(sp)
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; RV32I-NEXT: addi s0, sp, 112
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; RV32I-NEXT: addi a0, s0, -108
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; RV32I-NEXT: call notdead
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; RV32I-NEXT: lw a0, -8(s0)
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; RV32I-NEXT: lw a0, -8(a0)
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; RV32I-NEXT: lw a0, -8(a0)
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; RV32I-NEXT: lw s0, 104(sp)
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; RV32I-NEXT: lw ra, 108(sp)
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; RV32I-NEXT: addi sp, sp, 112
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_frameaddress_3_alloca:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -128
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; RV64I-NEXT: sd ra, 120(sp)
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; RV64I-NEXT: sd s0, 112(sp)
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; RV64I-NEXT: addi s0, sp, 128
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; RV64I-NEXT: addi a0, s0, -116
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; RV64I-NEXT: call notdead
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; RV64I-NEXT: ld a0, -16(s0)
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; RV64I-NEXT: ld a0, -16(a0)
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; RV64I-NEXT: ld a0, -16(a0)
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; RV64I-NEXT: ld s0, 112(sp)
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; RV64I-NEXT: ld ra, 120(sp)
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; RV64I-NEXT: addi sp, sp, 128
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; RV64I-NEXT: ret
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%1 = alloca [100 x i8]
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%2 = bitcast [100 x i8]* %1 to i8*
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call void @notdead(i8* %2)
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%3 = call i8* @llvm.frameaddress(i32 3)
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ret i8* %3
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}
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define i8* @test_returnaddress_0() nounwind {
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; RV32I-LABEL: test_returnaddress_0:
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; RV32I: # %bb.0:
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; RV32I-NEXT: mv a0, ra
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_returnaddress_0:
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; RV64I: # %bb.0:
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; RV64I-NEXT: mv a0, ra
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; RV64I-NEXT: ret
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%1 = call i8* @llvm.returnaddress(i32 0)
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ret i8* %1
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}
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define i8* @test_returnaddress_2() nounwind {
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; RV32I-LABEL: test_returnaddress_2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: lw a0, -8(s0)
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; RV32I-NEXT: lw a0, -8(a0)
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; RV32I-NEXT: lw a0, -4(a0)
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV64I-LABEL: test_returnaddress_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sd s0, 0(sp)
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; RV64I-NEXT: addi s0, sp, 16
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; RV64I-NEXT: ld a0, -16(s0)
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; RV64I-NEXT: ld a0, -16(a0)
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; RV64I-NEXT: ld a0, -8(a0)
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; RV64I-NEXT: ld s0, 0(sp)
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call i8* @llvm.returnaddress(i32 2)
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ret i8* %1
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}
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