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2d62ddc13c
As discussed in the RFC <http://lists.llvm.org/pipermail/llvm-dev/2018-October/126690.html>, 64-bit RISC-V has i64 as the only legal integer type. This patch introduces patterns to support codegen of the new instructions introduced in RV64I: addiw, addiw, subw, sllw, slliw, srlw, srliw, sraw, sraiw, ld, sd. Custom selection code is needed for srliw as SimplifyDemandedBits will remove lower bits from the mask, meaning the obvious pattern won't work: def : Pat<(sext_inreg (srl (and GPR:$rs1, 0xffffffff), uimm5:$shamt), i32), (SRLIW GPR:$rs1, uimm5:$shamt)>; This is sufficient to compile and execute all of the GCC torture suite for RV64I other than those files using frameaddr or returnaddr intrinsics (LegalizeDAG doesn't know how to promote the operands - a future patch addresses this). When promoting i32 sltu/sltiu operands, it would be more efficient to use sign-extension rather than zero-extension for RV64. A future patch adds a hook to allow this. Differential Revision: https://reviews.llvm.org/D52977 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@347973 91177308-0d34-0410-b5e6-96231b3b80d8
227 lines
5.6 KiB
LLVM
227 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; Check indexed and unindexed, sext, zext and anyext loads
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define i64 @lb(i8 *%a) nounwind {
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; RV64I-LABEL: lb:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lb a1, 0(a0)
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; RV64I-NEXT: lb a0, 1(a0)
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; RV64I-NEXT: ret
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%1 = getelementptr i8, i8* %a, i32 1
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%2 = load i8, i8* %1
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%3 = sext i8 %2 to i64
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; the unused load will produce an anyext for selection
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%4 = load volatile i8, i8* %a
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ret i64 %3
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}
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define i64 @lh(i16 *%a) nounwind {
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; RV64I-LABEL: lh:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lh a1, 0(a0)
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; RV64I-NEXT: lh a0, 4(a0)
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; RV64I-NEXT: ret
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%1 = getelementptr i16, i16* %a, i32 2
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%2 = load i16, i16* %1
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%3 = sext i16 %2 to i64
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; the unused load will produce an anyext for selection
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%4 = load volatile i16, i16* %a
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ret i64 %3
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}
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define i64 @lw(i32 *%a) nounwind {
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; RV64I-LABEL: lw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lw a1, 0(a0)
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; RV64I-NEXT: lw a0, 12(a0)
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; RV64I-NEXT: ret
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%1 = getelementptr i32, i32* %a, i32 3
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%2 = load i32, i32* %1
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%3 = sext i32 %2 to i64
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; the unused load will produce an anyext for selection
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%4 = load volatile i32, i32* %a
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ret i64 %3
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}
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define i64 @lbu(i8 *%a) nounwind {
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; RV64I-LABEL: lbu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lbu a1, 0(a0)
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; RV64I-NEXT: lbu a0, 4(a0)
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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%1 = getelementptr i8, i8* %a, i32 4
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%2 = load i8, i8* %1
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%3 = zext i8 %2 to i64
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%4 = load volatile i8, i8* %a
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%5 = zext i8 %4 to i64
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%6 = add i64 %3, %5
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ret i64 %6
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}
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define i64 @lhu(i16 *%a) nounwind {
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; RV64I-LABEL: lhu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lhu a1, 0(a0)
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; RV64I-NEXT: lhu a0, 10(a0)
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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%1 = getelementptr i16, i16* %a, i32 5
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%2 = load i16, i16* %1
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%3 = zext i16 %2 to i64
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%4 = load volatile i16, i16* %a
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%5 = zext i16 %4 to i64
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%6 = add i64 %3, %5
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ret i64 %6
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}
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define i64 @lwu(i32 *%a) nounwind {
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; RV64I-LABEL: lwu:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lwu a1, 0(a0)
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; RV64I-NEXT: lwu a0, 24(a0)
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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%1 = getelementptr i32, i32* %a, i32 6
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%2 = load i32, i32* %1
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%3 = zext i32 %2 to i64
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%4 = load volatile i32, i32* %a
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%5 = zext i32 %4 to i64
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%6 = add i64 %3, %5
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ret i64 %6
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}
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; Check indexed and unindexed stores
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define void @sb(i8 *%a, i8 %b) nounwind {
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; RV64I-LABEL: sb:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sb a1, 7(a0)
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; RV64I-NEXT: sb a1, 0(a0)
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; RV64I-NEXT: ret
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store i8 %b, i8* %a
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%1 = getelementptr i8, i8* %a, i32 7
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store i8 %b, i8* %1
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ret void
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}
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define void @sh(i16 *%a, i16 %b) nounwind {
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; RV64I-LABEL: sh:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sh a1, 16(a0)
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; RV64I-NEXT: sh a1, 0(a0)
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; RV64I-NEXT: ret
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store i16 %b, i16* %a
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%1 = getelementptr i16, i16* %a, i32 8
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store i16 %b, i16* %1
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ret void
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}
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define void @sw(i32 *%a, i32 %b) nounwind {
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; RV64I-LABEL: sw:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sw a1, 36(a0)
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; RV64I-NEXT: sw a1, 0(a0)
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; RV64I-NEXT: ret
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store i32 %b, i32* %a
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%1 = getelementptr i32, i32* %a, i32 9
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store i32 %b, i32* %1
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ret void
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}
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; 64-bit loads and stores
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define i64 @ld(i64 *%a) nounwind {
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; RV64I-LABEL: ld:
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; RV64I: # %bb.0:
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; RV64I-NEXT: ld a1, 0(a0)
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; RV64I-NEXT: ld a0, 80(a0)
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; RV64I-NEXT: ret
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%1 = getelementptr i64, i64* %a, i32 10
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%2 = load i64, i64* %1
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%3 = load volatile i64, i64* %a
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ret i64 %2
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}
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define void @sd(i64 *%a, i64 %b) nounwind {
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; RV64I-LABEL: sd:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sd a1, 88(a0)
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; RV64I-NEXT: sd a1, 0(a0)
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; RV64I-NEXT: ret
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store i64 %b, i64* %a
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%1 = getelementptr i64, i64* %a, i32 11
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store i64 %b, i64* %1
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ret void
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}
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; Check load and store to an i1 location
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define i64 @load_sext_zext_anyext_i1(i1 *%a) nounwind {
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; RV64I-LABEL: load_sext_zext_anyext_i1:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lb a1, 0(a0)
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; RV64I-NEXT: lbu a1, 1(a0)
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; RV64I-NEXT: lbu a0, 2(a0)
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; RV64I-NEXT: sub a0, a0, a1
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; RV64I-NEXT: ret
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; sextload i1
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%1 = getelementptr i1, i1* %a, i32 1
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%2 = load i1, i1* %1
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%3 = sext i1 %2 to i64
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; zextload i1
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%4 = getelementptr i1, i1* %a, i32 2
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%5 = load i1, i1* %4
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%6 = zext i1 %5 to i64
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%7 = add i64 %3, %6
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; extload i1 (anyext). Produced as the load is unused.
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%8 = load volatile i1, i1* %a
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ret i64 %7
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}
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define i16 @load_sext_zext_anyext_i1_i16(i1 *%a) nounwind {
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; RV64I-LABEL: load_sext_zext_anyext_i1_i16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lb a1, 0(a0)
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; RV64I-NEXT: lbu a1, 1(a0)
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; RV64I-NEXT: lbu a0, 2(a0)
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; RV64I-NEXT: sub a0, a0, a1
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; RV64I-NEXT: ret
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; sextload i1
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%1 = getelementptr i1, i1* %a, i32 1
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%2 = load i1, i1* %1
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%3 = sext i1 %2 to i16
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; zextload i1
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%4 = getelementptr i1, i1* %a, i32 2
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%5 = load i1, i1* %4
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%6 = zext i1 %5 to i16
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%7 = add i16 %3, %6
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; extload i1 (anyext). Produced as the load is unused.
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%8 = load volatile i1, i1* %a
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ret i16 %7
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}
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; Check load and store to a global
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@G = global i64 0
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define i64 @ld_sd_global(i64 %a) nounwind {
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; RV64I-LABEL: ld_sd_global:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a2, %hi(G)
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; RV64I-NEXT: ld a1, %lo(G)(a2)
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; RV64I-NEXT: sd a0, %lo(G)(a2)
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; RV64I-NEXT: addi a2, a2, %lo(G)
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; RV64I-NEXT: ld a3, 72(a2)
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; RV64I-NEXT: sd a0, 72(a2)
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: ret
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%1 = load volatile i64, i64* @G
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store i64 %a, i64* @G
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%2 = getelementptr i64, i64* @G, i64 9
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%3 = load volatile i64, i64* %2
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store i64 %a, i64* %2
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ret i64 %1
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}
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