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llvm/lib/Target/RISCV
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Sameer AbuAsal 78e3c70281 [RISCV] Add machine function pass to merge base + offset 
Summary:
   In r333455 we added a peephole to fix the corner cases that result
   from separating base + offset lowering of global address.The
   peephole didn't handle some of the cases because it only has a basic
   block view instead of a function level view.

   This patch replaces that logic with a machine function pass. In
   addition to handling the original cases it handles uses of the global
   address across blocks in function and folding an offset from LW\SW
   instruction. This pass won't run for OptNone compilation, so there
   will be a negative impact overall vs the old approach at O0.

Reviewers: asb, apazos, mgrang

Reviewed By: asb

Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones

Differential Revision: https://reviews.llvm.org/D47857

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@335786 91177308-0d34-0410-b5e6-96231b3b80d8
2018-06-27 20:51:42 +00:00
..
AsmParser
[RISCV] AsmParser support for the li pseudo instruction
2018-06-07 15:35:47 +00:00
Disassembler
Rename DEBUG macro to LLVM_DEBUG.
2018-05-14 12:53:11 +00:00
InstPrinter
[RISCV] Tablegen-driven Instruction Compression.
2018-04-06 21:07:05 +00:00
MCTargetDesc
[RISCV] Tail calls don't need to save return address
2018-06-21 14:37:09 +00:00
TargetInfo
Fix RISCV build after r318352
2017-11-16 18:39:31 +00:00
CMakeLists.txt
[RISCV] Add machine function pass to merge base + offset
2018-06-27 20:51:42 +00:00
LLVMBuild.txt
[RISCV] Initial codegen support for ALU operations
2017-10-19 21:37:38 +00:00
RISCV.h
[RISCV] Add machine function pass to merge base + offset
2018-06-27 20:51:42 +00:00
RISCV.td
[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation
2018-05-15 01:28:50 +00:00
RISCVAsmPrinter.cpp
Revert "[RISCV] implement li pseudo instruction"
2018-04-18 19:02:31 +00:00
RISCVCallingConv.td
[RISCV] Add custom CC_RISCV calling convention and improved call support
2017-12-11 12:49:02 +00:00
RISCVFrameLowering.cpp
[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
2018-03-20 01:39:17 +00:00
RISCVFrameLowering.h
[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
2018-03-20 01:39:17 +00:00
RISCVInstrFormats.td
[RISCV] AsmParser support for the li pseudo instruction
2018-06-07 15:35:47 +00:00
RISCVInstrFormatsC.td
[RISCV] MC layer support for the remaining RVC instructions
2017-12-13 09:32:55 +00:00
RISCVInstrInfo.cpp
[RISCV] Lower the tail pseudoinstruction
2018-05-23 22:44:08 +00:00
RISCVInstrInfo.h
[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot
2018-04-26 15:34:27 +00:00
RISCVInstrInfo.td
[RISCV] Add InstAlias definitions for sgt and sgtu
2018-06-20 12:54:02 +00:00
RISCVInstrInfoA.td
[RISCV] Add codegen support for atomic load/stores with RV32A
2018-06-13 12:04:51 +00:00
RISCVInstrInfoC.td
[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0
2018-04-12 19:22:40 +00:00
RISCVInstrInfoD.td
[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}
2018-06-20 14:03:02 +00:00
RISCVInstrInfoF.td
[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w
2018-06-20 18:42:25 +00:00
RISCVInstrInfoM.td
[RISCV] Codegen support for the standard RV32M instruction set extension
2018-01-18 12:36:38 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Add machine function pass to merge base + offset
2018-06-27 20:51:42 +00:00
RISCVISelLowering.cpp
[RISCV] Add codegen support for atomic load/stores with RV32A
2018-06-13 12:04:51 +00:00
RISCVISelLowering.h
[RISCV] Add codegen support for atomic load/stores with RV32A
2018-06-13 12:04:51 +00:00
RISCVMachineFunctionInfo.h
[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
2018-04-12 05:34:25 +00:00
RISCVMCInstLower.cpp
[RISCV] Add codegen for RV32F floating point load/store
2018-03-20 13:26:12 +00:00
RISCVMergeBaseOffset.cpp
[RISCV] Add machine function pass to merge base + offset
2018-06-27 20:51:42 +00:00
RISCVRegisterInfo.cpp
[RISCV] Set isReMaterializable on ADDI and LUI instructions
2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.h
[RISCV] Set isReMaterializable on ADDI and LUI instructions
2018-05-17 15:51:37 +00:00
RISCVRegisterInfo.td
[RISCV] Lower the tail pseudoinstruction
2018-05-23 22:44:08 +00:00
RISCVSubtarget.cpp
[RISCV] Initial codegen support for ALU operations
2017-10-19 21:37:38 +00:00
RISCVSubtarget.h
[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation
2018-05-15 01:28:50 +00:00
RISCVTargetMachine.cpp
[RISCV] Add machine function pass to merge base + offset
2018-06-27 20:51:42 +00:00
RISCVTargetMachine.h
[RISCV] Initial codegen support for ALU operations
2017-10-19 21:37:38 +00:00
RISCVTargetObjectFile.cpp
[RISCV] Use init_array instead of ctors for RISCV target, by default
2018-03-24 18:37:19 +00:00
RISCVTargetObjectFile.h
[RISCV] Use init_array instead of ctors for RISCV target, by default
2018-03-24 18:37:19 +00:00