Sander de Smalen cf59225a2b [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors. ...

Summary:
Add a register class for SVE predicate operands that can only be p0-p7 (as opposed to p0-p15)

Patch [1/3] in a series to add predicated ADD/SUB instructions for SVE.

Reviewers: rengolin, mcrosier, evandro, fhahn, echristo, olista01, SjoerdMeijer, javed.absar

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41441

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321699 91177308-0d34-0410-b5e6-96231b3b80d8

2018-01-03 10:15:46 +00:00

..

AArch64Disassembler.cpp

[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.

2018-01-03 10:15:46 +00:00

AArch64Disassembler.h

[AArch64, Lanai] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

2017-01-06 00:30:53 +00:00

AArch64ExternalSymbolizer.cpp

Untabify.

2016-06-20 00:37:41 +00:00

AArch64ExternalSymbolizer.h

Reflect the MC/MCDisassembler split on the include/ level.

2016-01-26 16:44:37 +00:00

CMakeLists.txt

Remove outdated CMake MSVC workaround

2014-06-08 07:37:17 +00:00

LLVMBuild.txt

[AArch64] Add v8.1a atomic instructions

2015-06-02 10:58:41 +00:00