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Two issues found when doing codegen for splitting vector with non-zero alloca addr space: DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT/SplitVecOp_EXTRACT_VECTOR_ELT uses dummy pointer info for creating SDStore. Since one pointer operand contains multiply and add, InferPointerInfo is unable to infer the correct pointer info, which ends up with a dummy pointer info for the target to lower store and results in isel failure. The fix is to introduce MachinePointerInfo::getUnknownStack to represent MachinePointerInfo which is known in alloca address space but without other information. TargetLowering::getVectorElementPointer uses value type of pointer in addr space 0 for multiplication of index and then add it to the pointer. However the pointer may be in an addr space which has different size than addr space 0. The fix is to use the pointer value type for index multiplication. Differential Revision: https://reviews.llvm.org/D39758 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319622 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
1.2 KiB
LLVM
25 lines
1.2 KiB
LLVM
; RUN: llc -debug-only=machine-scheduler -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs %s -o - 2>&1| FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC -check-prefix=DEBUG %s
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target datalayout = "A5"
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; REQUIRES: asserts
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; Verify that the extload generated from %eval has the default
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; alignment size (2) corresponding to the underlying memory size (i16)
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; size and not 4 corresponding to the sign-extended size (i32).
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; DEBUG: {{^}}# Machine code for function extload_align:
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; DEBUG: mem:LD2[<unknown>(addrspace=5)]{{[^(]}}
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; DEBUG: {{^}}# End machine code for function extload_align.
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define amdgpu_kernel void @extload_align(i32 addrspace(5)* %out, i32 %index) #0 {
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%v0 = alloca [4 x i16], addrspace(5)
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%a1 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 0
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%a2 = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 1
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store i16 0, i16 addrspace(5)* %a1
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store i16 1, i16 addrspace(5)* %a2
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%a = getelementptr inbounds [4 x i16], [4 x i16] addrspace(5)* %v0, i32 0, i32 %index
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%val = load i16, i16 addrspace(5)* %a
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%eval = sext i16 %val to i32
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store i32 %eval, i32 addrspace(5)* %out
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ret void
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}
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