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https://github.com/RPCS3/llvm.git
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2e48864110
Try to avoid mutually exclusive features. Don't use a real default GPU, and use a fake "generic". The goal is to make it easier to see which set of features are incompatible between feature strings. Most of the test changes are due to random scheduling changes from not having a default fullspeed model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310258 91177308-0d34-0410-b5e6-96231b3b80d8
284 lines
8.9 KiB
LLVM
284 lines
8.9 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}v_sad_u32_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%t0 = select i1 %icmp0, i32 %a, i32 %b
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%icmp1 = icmp ule i32 %a, %b
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%t1 = select i1 %icmp1, i32 %a, i32 %b
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%ret0 = sub i32 %t0, %t1
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_constant_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 20
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define amdgpu_kernel void @v_sad_u32_constant_pat1(i32 addrspace(1)* %out, i32 %a) {
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%icmp0 = icmp ugt i32 %a, 90
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%t0 = select i1 %icmp0, i32 %a, i32 90
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%icmp1 = icmp ule i32 %a, 90
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%t1 = select i1 %icmp1, i32 %a, i32 90
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%ret0 = sub i32 %t0, %t1
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%ret = add i32 %ret0, 20
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_pat2:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%sub0 = sub i32 %a, %b
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%sub1 = sub i32 %b, %a
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%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat1:
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; GCN: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: s_min_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%t0 = select i1 %icmp0, i32 %a, i32 %b
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%icmp1 = icmp ule i32 %a, %b
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%t1 = select i1 %icmp1, i32 %a, i32 %b
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%ret0 = sub i32 %t0, %t1
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store volatile i32 %ret0, i32 *undef
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_multi_use_add_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%t0 = select i1 %icmp0, i32 %a, i32 %b
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%icmp1 = icmp ule i32 %a, %b
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%t1 = select i1 %icmp1, i32 %a, i32 %b
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%ret0 = sub i32 %t0, %t1
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%ret = add i32 %ret0, %c
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store volatile i32 %ret, i32 *undef
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_multi_use_max_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%t0 = select i1 %icmp0, i32 %a, i32 %b
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store volatile i32 %t0, i32 *undef
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%icmp1 = icmp ule i32 %a, %b
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%t1 = select i1 %icmp1, i32 %a, i32 %b
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%ret0 = sub i32 %t0, %t1
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_multi_use_min_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%t0 = select i1 %icmp0, i32 %a, i32 %b
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%icmp1 = icmp ule i32 %a, %b
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%t1 = select i1 %icmp1, i32 %a, i32 %b
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store volatile i32 %t1, i32 *undef
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%ret0 = sub i32 %t0, %t1
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat2:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%sub0 = sub i32 %a, %b
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store volatile i32 %sub0, i32 *undef
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%sub1 = sub i32 %b, %a
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%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2:
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; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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; GCN-DAG: v_cmp_gt_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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%icmp0 = icmp ugt i32 %a, %b
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%sub0 = sub i32 %a, %b
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%sub1 = sub i32 %b, %a
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%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
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store volatile i32 %ret0, i32 *undef
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_vector_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_vector_pat1(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%icmp0 = icmp ugt <4 x i32> %a, %b
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%t0 = select <4 x i1> %icmp0, <4 x i32> %a, <4 x i32> %b
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%icmp1 = icmp ule <4 x i32> %a, %b
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%t1 = select <4 x i1> %icmp1, <4 x i32> %a, <4 x i32> %b
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%ret0 = sub <4 x i32> %t0, %t1
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%ret = add <4 x i32> %ret0, %c
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store <4 x i32> %ret, <4 x i32> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_vector_pat2:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_vector_pat2(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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%icmp0 = icmp ugt <4 x i32> %a, %b
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%sub0 = sub <4 x i32> %a, %b
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%sub1 = sub <4 x i32> %b, %a
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%ret0 = select <4 x i1> %icmp0, <4 x i32> %sub0, <4 x i32> %sub1
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%ret = add <4 x i32> %ret0, %c
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store <4 x i32> %ret, <4 x i32> addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_i16_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_i16_pat1(i16 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
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%icmp0 = icmp ugt i16 %a, %b
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%t0 = select i1 %icmp0, i16 %a, i16 %b
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%icmp1 = icmp ule i16 %a, %b
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%t1 = select i1 %icmp1, i16 %a, i16 %b
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%ret0 = sub i16 %t0, %t1
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%ret = add i16 %ret0, %c
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store i16 %ret, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_i16_pat2:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_i16_pat2(i16 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b, i16 zeroext %c) {
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%icmp0 = icmp ugt i16 %a, %b
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%sub0 = sub i16 %a, %b
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%sub1 = sub i16 %b, %a
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%ret0 = select i1 %icmp0, i16 %sub0, i16 %sub1
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%ret = add i16 %ret0, %c
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store i16 %ret, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_i8_pat1:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_i8_pat1(i8 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
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%icmp0 = icmp ugt i8 %a, %b
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%t0 = select i1 %icmp0, i8 %a, i8 %b
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%icmp1 = icmp ule i8 %a, %b
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%t1 = select i1 %icmp1, i8 %a, i8 %b
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%ret0 = sub i8 %t0, %t1
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%ret = add i8 %ret0, %c
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store i8 %ret, i8 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_i8_pat2:
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; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_i8_pat2(i8 addrspace(1)* %out, i8 zeroext %a, i8 zeroext %b, i8 zeroext %c) {
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%icmp0 = icmp ugt i8 %a, %b
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%sub0 = sub i8 %a, %b
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%sub1 = sub i8 %b, %a
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%ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1
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%ret = add i8 %ret0, %c
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store i8 %ret, i8 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat1:
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; GCN: v_cmp_le_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GCN: s_max_u32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: v_sub_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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%icmp0 = icmp ugt i32 %a, %b
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%t0 = select i1 %icmp0, i32 %a, i32 %b
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%icmp1 = icmp ule i32 %a, %b
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%t1 = select i1 %icmp1, i32 %a, i32 %d
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%ret0 = sub i32 %t0, %t1
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_sad_u32_mismatched_operands_pat2:
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; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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; GCN: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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%icmp0 = icmp ugt i32 %a, %b
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%sub0 = sub i32 %a, %d
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%sub1 = sub i32 %b, %a
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%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
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%ret = add i32 %ret0, %c
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store i32 %ret, i32 addrspace(1)* %out
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ret void
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}
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