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ff43d39338
This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320797 91177308-0d34-0410-b5e6-96231b3b80d8
129 lines
3.4 KiB
LLVM
129 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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define void @foo(i32 %a, i32 *%b, i1 %c) {
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; RV32I-LABEL: foo:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: sw s0, 8(sp)
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; RV32I-NEXT: addi s0, sp, 16
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: beq a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_1
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; RV32I-NEXT: .LBB0_1: # %test2
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bne a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_2
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; RV32I-NEXT: .LBB0_2: # %test3
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: blt a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_3
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; RV32I-NEXT: .LBB0_3: # %test4
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bge a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_4
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; RV32I-NEXT: .LBB0_4: # %test5
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bltu a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_5
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; RV32I-NEXT: .LBB0_5: # %test6
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bgeu a3, a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_6
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; RV32I-NEXT: .LBB0_6: # %test7
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: blt a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_7
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; RV32I-NEXT: .LBB0_7: # %test8
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bge a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_8
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; RV32I-NEXT: .LBB0_8: # %test9
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bltu a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_9
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; RV32I-NEXT: .LBB0_9: # %test10
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; RV32I-NEXT: lw a3, 0(a1)
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; RV32I-NEXT: bgeu a0, a3, .LBB0_12
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; RV32I-NEXT: j .LBB0_10
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; RV32I-NEXT: .LBB0_10: # %test11
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: andi a0, a2, 1
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; RV32I-NEXT: bnez a0, .LBB0_12
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; RV32I-NEXT: j .LBB0_11
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; RV32I-NEXT: .LBB0_11: # %test12
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; RV32I-NEXT: lw a0, 0(a1)
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; RV32I-NEXT: .LBB0_12: # %end
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; RV32I-NEXT: lw s0, 8(sp)
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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%val1 = load volatile i32, i32* %b
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%tst1 = icmp eq i32 %val1, %a
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br i1 %tst1, label %end, label %test2
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test2:
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%val2 = load volatile i32, i32* %b
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%tst2 = icmp ne i32 %val2, %a
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br i1 %tst2, label %end, label %test3
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test3:
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%val3 = load volatile i32, i32* %b
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%tst3 = icmp slt i32 %val3, %a
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br i1 %tst3, label %end, label %test4
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test4:
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%val4 = load volatile i32, i32* %b
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%tst4 = icmp sge i32 %val4, %a
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br i1 %tst4, label %end, label %test5
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test5:
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%val5 = load volatile i32, i32* %b
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%tst5 = icmp ult i32 %val5, %a
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br i1 %tst5, label %end, label %test6
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test6:
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%val6 = load volatile i32, i32* %b
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%tst6 = icmp uge i32 %val6, %a
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br i1 %tst6, label %end, label %test7
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; Check for condition codes that don't have a matching instruction
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test7:
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%val7 = load volatile i32, i32* %b
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%tst7 = icmp sgt i32 %val7, %a
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br i1 %tst7, label %end, label %test8
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test8:
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%val8 = load volatile i32, i32* %b
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%tst8 = icmp sle i32 %val8, %a
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br i1 %tst8, label %end, label %test9
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test9:
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%val9 = load volatile i32, i32* %b
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%tst9 = icmp ugt i32 %val9, %a
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br i1 %tst9, label %end, label %test10
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test10:
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%val10 = load volatile i32, i32* %b
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%tst10 = icmp ule i32 %val10, %a
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br i1 %tst10, label %end, label %test11
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; Check the case of a branch where the condition was generated in another
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; function
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test11:
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%val11 = load volatile i32, i32* %b
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br i1 %c, label %end, label %test12
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test12:
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%val12 = load volatile i32, i32* %b
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br label %end
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end:
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ret void
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}
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