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0749c8e439
This patch ensures that we actually scalarize instructions marked scalar after vectorization. Previously, such instructions may have been vectorized instead. Differential Revision: https://reviews.llvm.org/D23889 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282418 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
2.9 KiB
LLVM
75 lines
2.9 KiB
LLVM
; RUN: opt < %s -force-vector-width=4 -force-vector-interleave=2 -loop-vectorize -instcombine -S | FileCheck %s
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; RUN: opt < %s -force-vector-width=4 -force-vector-interleave=2 -loop-vectorize -S | FileCheck %s --check-prefix=NO-IC
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target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
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; CHECK-LABEL: @scalar_after_vectorization_0
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;
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; CHECK: vector.body:
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; CHECK: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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; CHECK: %offset.idx = or i64 %index, 1
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; CHECK: %[[T2:.+]] = add nuw nsw i64 %offset.idx, %tmp0
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; CHECK: %[[T3:.+]] = sub nsw i64 %[[T2]], %x
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; CHECK: %[[T4:.+]] = getelementptr inbounds i32, i32* %a, i64 %[[T3]]
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; CHECK: %[[T5:.+]] = bitcast i32* %[[T4]] to <4 x i32>*
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; CHECK: load <4 x i32>, <4 x i32>* %[[T5]], align 4
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; CHECK: %[[T6:.+]] = getelementptr i32, i32* %[[T4]], i64 4
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; CHECK: %[[T7:.+]] = bitcast i32* %[[T6]] to <4 x i32>*
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; CHECK: load <4 x i32>, <4 x i32>* %[[T7]], align 4
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; CHECK: br {{.*}}, label %middle.block, label %vector.body
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;
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; NO-IC-LABEL: @scalar_after_vectorization_0
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;
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; NO-IC: vector.body:
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; NO-IC: %index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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; NO-IC: %offset.idx = add i64 1, %index
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; NO-IC: %[[T2:.+]] = add i64 %offset.idx, 0
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; NO-IC: %[[T3:.+]] = add i64 %offset.idx, 4
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; NO-IC: %[[T4:.+]] = add nuw nsw i64 %[[T2]], %tmp0
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; NO-IC: %[[T5:.+]] = add nuw nsw i64 %[[T3]], %tmp0
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; NO-IC: %[[T6:.+]] = sub nsw i64 %[[T4]], %x
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; NO-IC: %[[T7:.+]] = sub nsw i64 %[[T5]], %x
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; NO-IC: %[[T8:.+]] = getelementptr inbounds i32, i32* %a, i64 %[[T6]]
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; NO-IC: %[[T9:.+]] = getelementptr inbounds i32, i32* %a, i64 %[[T7]]
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; NO-IC: %[[T10:.+]] = getelementptr i32, i32* %[[T8]], i32 0
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; NO-IC: %[[T11:.+]] = bitcast i32* %[[T10]] to <4 x i32>*
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; NO-IC: load <4 x i32>, <4 x i32>* %[[T11]], align 4
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; NO-IC: %[[T12:.+]] = getelementptr i32, i32* %[[T8]], i32 4
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; NO-IC: %[[T13:.+]] = bitcast i32* %[[T12]] to <4 x i32>*
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; NO-IC: load <4 x i32>, <4 x i32>* %[[T13]], align 4
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; NO-IC: br {{.*}}, label %middle.block, label %vector.body
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;
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define void @scalar_after_vectorization_0(i32* noalias %a, i32* noalias %b, i64 %x, i64 %y) {
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outer.ph:
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br label %outer.body
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outer.body:
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%i = phi i64 [ 1, %outer.ph ], [ %i.next, %inner.end ]
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%tmp0 = mul nuw nsw i64 %i, %x
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br label %inner.ph
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inner.ph:
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br label %inner.body
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inner.body:
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%j = phi i64 [ 1, %inner.ph ], [ %j.next, %inner.body ]
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%tmp1 = add nuw nsw i64 %j, %tmp0
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%tmp2 = sub nsw i64 %tmp1, %x
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%tmp3 = getelementptr inbounds i32, i32* %a, i64 %tmp2
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%tmp4 = load i32, i32* %tmp3, align 4
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%tmp5 = getelementptr inbounds i32, i32* %b, i64 %tmp1
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store i32 %tmp4, i32* %tmp5, align 4
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%j.next = add i64 %j, 1
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%cond.j = icmp slt i64 %j.next, %y
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br i1 %cond.j, label %inner.body, label %inner.end
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inner.end:
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%i.next = add i64 %i, 1
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%cond.i = icmp slt i64 %i.next, %y
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br i1 %cond.i, label %outer.body, label %outer.end
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outer.end:
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ret void
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}
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