mirror of
https://github.com/RPCS3/llvm.git
synced 2026-08-28 05:10:05 -04:00
Matt Arsenault
e536396218
------------------------------------------------------------------------ r292982 | arsenm | 2017-01-24 14:02:15 -0800 (Tue, 24 Jan 2017) | 8 lines Enable FeatureFlatForGlobal on Volcanic Islands This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293326 91177308-0d34-0410-b5e6-96231b3b80d8
72 lines
3.0 KiB
LLVM
72 lines
3.0 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone
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declare <2 x i32> @llvm.cttz.v2i32(<2 x i32>, i1) nounwind readnone
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declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1) nounwind readnone
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; FUNC-LABEL: {{^}}s_cttz_zero_undef_i32:
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; SI: s_load_dword [[VAL:s[0-9]+]],
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; SI: s_ff1_i32_b32 [[SRESULT:s[0-9]+]], [[VAL]]
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; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
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; SI: buffer_store_dword [[VRESULT]],
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define void @s_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
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store i32 %cttz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_i32:
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; SI: buffer_load_dword [[VAL:v[0-9]+]],
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; SI: v_ffbl_b32_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; SI: buffer_store_dword [[RESULT]],
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define void @v_cttz_zero_undef_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind {
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%val = load i32, i32 addrspace(1)* %valptr, align 4
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%cttz = call i32 @llvm.cttz.i32(i32 %val, i1 true) nounwind readnone
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store i32 %cttz, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_v2i32:
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; SI: buffer_load_dwordx2
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: buffer_store_dwordx2
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define void @v_cttz_zero_undef_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrspace(1)* noalias %valptr) nounwind {
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%val = load <2 x i32>, <2 x i32> addrspace(1)* %valptr, align 8
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%cttz = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %val, i1 true) nounwind readnone
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store <2 x i32> %cttz, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_cttz_zero_undef_v4i32:
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; SI: buffer_load_dwordx4
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: v_ffbl_b32_e32
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; SI: buffer_store_dwordx4
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; SI: s_endpgm
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}}
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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; EG: FFBL_INT {{\*? *}}[[RESULT]]
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define void @v_cttz_zero_undef_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %valptr) nounwind {
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%val = load <4 x i32>, <4 x i32> addrspace(1)* %valptr, align 16
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%cttz = call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %val, i1 true) nounwind readnone
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store <4 x i32> %cttz, <4 x i32> addrspace(1)* %out, align 16
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ret void
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}
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