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https://github.com/RPCS3/llvm.git
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Matt Arsenault
e536396218
------------------------------------------------------------------------ r292982 | arsenm | 2017-01-24 14:02:15 -0800 (Tue, 24 Jan 2017) | 8 lines Enable FeatureFlatForGlobal on Volcanic Islands This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@293326 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.7 KiB
LLVM
71 lines
2.7 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; GCN-LABEL: {{^}}fpext_f16_to_f32
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: v_cvt_f32_f16_e32 v[[R_F32:[0-9]+]], v[[A_F16]]
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; GCN: buffer_store_dword v[[R_F32]]
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; GCN: s_endpgm
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define void @fpext_f16_to_f32(
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float addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = fpext half %a.val to float
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store float %r.val, float addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fpext_f16_to_f64
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; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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; GCN: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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; GCN: v_cvt_f64_f32_e32 v{{\[}}[[R_F64_0:[0-9]+]]:[[R_F64_1:[0-9]+]]{{\]}}, v[[A_F32]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[R_F64_0]]:[[R_F64_1]]{{\]}}
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; GCN: s_endpgm
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define void @fpext_f16_to_f64(
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double addrspace(1)* %r,
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half addrspace(1)* %a) {
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entry:
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%a.val = load half, half addrspace(1)* %a
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%r.val = fpext half %a.val to double
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store double %r.val, double addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fpext_v2f16_to_v2f32
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; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; VI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; GCN: v_cvt_f32_f16_e32 v[[R_F32_0:[0-9]+]], v[[A_V2_F16]]
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; SI: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; GCN: v_cvt_f32_f16_e32 v[[R_F32_1:[0-9]+]], v[[A_F16_1]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[R_F32_0]]:[[R_F32_1]]{{\]}}
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; GCN: s_endpgm
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define void @fpext_v2f16_to_v2f32(
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<2 x float> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%r.val = fpext <2 x half> %a.val to <2 x float>
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store <2 x float> %r.val, <2 x float> addrspace(1)* %r
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ret void
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}
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; GCN-LABEL: {{^}}fpext_v2f16_to_v2f64
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; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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; GCN: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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; GCN: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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; GCN: v_cvt_f64_f32_e32 v{{\[}}{{[0-9]+}}:[[R_F64_3:[0-9]+]]{{\]}}, v[[A_F32_1]]
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; GCN: v_cvt_f64_f32_e32 v{{\[}}[[R_F64_0:[0-9]+]]:{{[0-9]+}}{{\]}}, v[[A_F32_0]]
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; GCN: buffer_store_dwordx4 v{{\[}}[[R_F64_0]]:[[R_F64_3]]{{\]}}
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; GCN: s_endpgm
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define void @fpext_v2f16_to_v2f64(
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<2 x double> addrspace(1)* %r,
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<2 x half> addrspace(1)* %a) {
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entry:
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%r.val = fpext <2 x half> %a.val to <2 x double>
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store <2 x double> %r.val, <2 x double> addrspace(1)* %r
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ret void
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}
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